SRAM memory is an ideal vehicle for defect monitoring and yield improvement during process development because of its highly structured architecture. However, the success rate of defect detection, especially for soft single-column failures, is decreasing when traditional physical failure analysis (PFA) with only the bitmap is available for guidance. This is due to a variety of invisible or undetectable defects that cause leakage in the device. In order to understand the leakage behavior in advanced high voltage (HV) processes, a Conductive Atomic Force Microscope (C-AFM) [1-4] is introduced to perform junction-level fault isolation prior to attempting PFA. According to J. P. Morniroli [5], crystalline defects affect convergent-beam electron diffraction (CBED) and large angle convergent-beam electron diffraction (LACBED) patterns, so CBED and LACBED techniques were also applied to the specimens containing dislocations to allow further characterization of these defects. In this study quantified data extracted using the C-AFM is also used to establish a connection between the failure mechanism discovered and the soft single column failure mode.

In order to do the failure analysis on flip chip connected with ceramic substrate, solder bump should be completely removed from chip surface. The die soldered on ceramic substrate of flip chip package is likely damaged during the removing process for the high etching and abrasion resistance of ceramic substrate as well as the poor uniformity of mechanical polish. In this paper, a thermal method for the decapsulation of flip chip package is developed, which included heat sink removal, ceramic substrate and solder bump separation, and solder residue clean out from the chip surface. In the last step, three temperature levels of H2N2O6 – H2O (fuming Nitric acid) were selected for the removal of eutectic, high-lead and lead free solders, respectively.

Thermal fatigue cracking of lead-free solder joints within flipchip packages was investigated in this study by using scanning acoustic microscope (SAM) and SEM. The distribution of substrate delaminations was mapped with SAM of high depth resolution and observed in cross-section with SEM to find the mechanism of crack growth during thermal reliability tests. The study revealed that the interfacial crack always initiated from the pad edge. This is attributed to the coefficient of thermal expansion (CTE) mismatch between underfill and the PCB substrate. The propagation of fatigue crack within solder joint is closely related to the morphology of interfacial/intergranular intermetallic compound (IMC) formed at the elevated temperature of thermal cycle.

Strained silicon induced by the CMOS device process has been considered an important technology for improving the performance of MOSFETs by increasing local carrier mobility in the current channel. In order to evaluate the feasibility of using convergent beam electron diffraction (CBED) in lattice strain determination, high-order Laue zone (HOLZ) lines inside the center disc of a CBED pattern with specific zone axes were kinematically simulated. The intersecting HOLZ lines shift was plotted against the lattice parameter for the determination of uniaxial strain.