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Tsai Tony
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Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 177-181, November 15–19, 2009,
Abstract
View Papertitled, A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication
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for content titled, A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication
As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 289-292, November 15–19, 2009,
Abstract
View Papertitled, Studies on a Qualification Method (OSAT) of Microchip Al Bondpads in Wafer Fabrication
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for content titled, Studies on a Qualification Method (OSAT) of Microchip Al Bondpads in Wafer Fabrication
Non-stick on pad (NSOP) is a yield limiting factor that can occur due to various reasons such as particle contamination, galvanic corrosion, Fluorine-induced corrosion, process anomalies, etc. The problem of NSOP can be mitigated through a careful process characterization and optimization. In this paper, a bondpad qualification methodology (OSAT) will be discussed. It will be argued that by employing different physical analysis techniques in a failure analysis of wafer fabrication, it is possible to perform comprehensive characterization studies of the Aluminum bondpad so as to develop a robust far backend of line process. A good quality Al bondpad must meet the following four conditions-OSAT: (i) it should be no discoloration (using Optical inspection); (ii) should be defect free (using SEM inspection); (iii) should be with low contamination level (such as fluorine and carbon contamination should be within a control limit) (using Auger analysis) and (iv) should have a protective layer on bondpad surface so as to prevent bondpad corrosion (using TEM).