Presentation slides for the ISTFA 2024 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques (2024 Update).”

We demonstrate the effectiveness of combining top-down and cross-sectional electron beam induced current (EBIC) imaging with SEM nanoprobe analysis to identify subtle front-end defects in advanced FinFET technology. Our approach successfully localized a novel fin nanocrack defect that had previously eluded detection through conventional TEM imaging. This systematic resistive pMOS failure, observable only in memory arrays at 150°C, exemplifies the power of EBIC as an alternative to scanning capacitance microscopy for detecting dopant anomalies and subtle defects. The sample preparation and EBIC methodologies presented here are broadly applicable across CMOS technologies, offering a versatile approach to defect analysis.

In the field of failure analysis (FA) for semiconductor devices, the transmission electron microscope (TEM) as an analytical tool is integral to finding visible evidence of defects and their root cause. Especially as device features shrink, imaging and analyzing increasingly subtle defects requires detailed elemental analysis. In this work, elemental analysis using an aberration-corrected TEM at different accelerating voltages (200 kV and 80 kV) is discussed. The impact of accelerating voltage on elemental analysis with regards to Electron Energy Loss Spectroscopy (EELS) and Energy Dispersive X-Ray Spectroscopy (EDS) is of central focus. Two case studies involving TEM samples of different thicknesses are presented that clearly indicate important differences in the analytical data collected at different accelerating voltages. The work revealed that for elemental analysis of thick TEM samples (100 nm and over) 200 kV is preferred, and for thin samples, 80 kV provides superior signal in EDS and EELS.

As integrated circuit (IC) feature dimensions have shrunk, the need for precise and repeatable sample preparation techniques has increased. In this work, the process of preparation of ultrathin planar-to-cross-section conversion transmission electron microscopy (TEM) samples using a gallium dual-column focused ion beam (FIB)/scanning electron microscope (SEM) system is examined. Sample preparation technique in this paper is aimed at repeatably isolating features in the 5-30 nm range, while limiting common issues such as amorphization, lamella warpage, and the curtain effect (or “curtaining”). This can be achieved through careful selection of FIB parameters including ion beam energy, ion beam current, stage tilt, and deposited protective layer materials and thicknesses, which are all discussed in this work.

In this work, we present three case studies that highlight the novelty and effectiveness of using multiple plasma FIB trenches to simultaneously access multiple metal layers for nanoprobing failure analysis. Multilayer access enabled otherwise impossible two-tip current imaging techniques and allowed us to fully characterize suspect logic gate transistors by exposing internal nodes, while preserving higher metal inputs and outputs. The presented case studies focus on late node planar and established FinFET technologies. The delayering techniques used are not necessarily technology dependent, but highly scaled and advanced processes generally require smaller trench areas for multilayer access. The minimum trench dimensions are limited by ion beam imaging resolution and trench-nanoprobe tip geometry.

Presentation slides for the ISTFA 2023 Tutorial session “TEM Techniques for Semiconductor Failure Analysis.”

Presentation slides for the ISTFA 2023 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques.”

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.

Visualization of dopant related anomalies in integrated circuits is extremely challenging. Cleaving of the die may not be possible in practical failure analysis situations that require extensive electrical fault isolation, where the failing die can be submitted of scanning probe microscopy analysis in various states such as partially depackaged die, backside thinned die, and so on. In advanced technologies, the circuit orientation in the wafer may not align with preferred crystallographic direction for cleaving the silicon or other substrates. In order to overcome these issues, a focused ion beam lift-out based approach for site-specific cross-section sample preparation is developed in this work. A directional mechanical polishing procedure to produce smooth damage-free surface for junction profiling is also implemented. Two failure analysis applications of the sample preparation method to visualize junction anomalies using scanning microwave microscopy are also discussed.

Transmission electron microscope based elemental analysis techniques utilize X-ray photons in EDS and inelastically scattered electrons or the energy-loss electrons in electron energy-loss spectroscopy and energy-filtered transmission electron microscopy (EFTEM). This paper discusses the applications of EFTEM to visualize polysilicon defects, gate dielectric and silicon nanocrystals using inelastically scattered low energy-loss electrons. It focuses on features that are primarily composed of silicon and silicon-oxide. Various benefits of using plasmon energy-loss electrons to image silicon nanocrystals layer in thin film storage device are also outlined. Even though this work has focused on low-loss imaging of features and defects in the front-end of the process based on silicon/silicon-oxide integrated circuits, these techniques can also be applied to technologies based on other materials by selecting appropriate plasmon peaks corresponding to those materials.

As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.

This paper outlines the analysis of a flash single bit failure caused by bitcell degradation over write/erase cycling. With no physical anomaly present at the failing single bit, Atomic Force Probing (AFP) characterization was utilized in conjunction with thermal response characterization to direct analysis towards a particular non-visible defect as the root cause. Existence of the hypothesized non-visible defect causing the single bit cycling failure was proven through Transmission Electron Microscopy (TEM) stained sample analysis, which highlighted an anomalous lateral drain junction formation at the single bit that caused the cycling failure.

This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.