Presentation slides for the ISTFA 2024 Tutorial session “Analog Simulation and Fault Simulation for Failure Analysis of Analog Circuits.”

The localization of defects that cause dynamic electrical behavior is a constant challenge for failure analysts. Such types of failures are often present in analog circuits, and standard fault isolation techniques are constrained and not always successful. In this paper, we demonstrate a method to exploit industrial fault simulators in conjunction with standard analysis methods to solve analyses in analog circuits. In addition, we will show methods to adapt fault simulation to these dynamic electrical failure modes. Successful fault isolation results from real-world failure analyses of oscillators, which are typical inside analog and mixed-signal circuits.

Getting accurate fault isolation during failure analysis is mandatory for success of Physical Failure Analysis (PFA) in critical applications. Unfortunately, achieving such accuracy is becoming more and more difficult with today’s diagnosis tools and actual process node such as BCD9 and FinFET 7 nm, compromising the success of subsequent PFA done on defective SoCs. Electrical simulation is used to reproduce emission microscopy, in our previous work and, in this paper, we demonstrate the possibility of using fault simulation tools with the results of electrical test and fault isolation techniques to provide diagnosis with accurate candidates for physical analysis. The experimental results of the presented flow, from several cases of application, show the validity of this approach.

This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.