This paper demonstrates that e-beam assisted device alteration (EADA) is a powerful, high-resolution technique for fault isolation debug for advanced technology nodes. A case study using this technique is reviewed and shows successful isolation of a defective single inverter. In addition, fundamental studies of ring oscillator behavior and device perturbations with e-beam exposure found clear correlations for electron beam exposure with NMOS/PMOS device parameters. Electron-hole pair generation in the device with beam exposure is likely the main component for the perturbation, but there may be other contributing factors including charging effects and/or heating.

With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.

This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

On older semiconductor technology, electron-beam probing (EBP) for active voltage contrast and waveform on frontside metal lines was widely utilized. EBP is also being extended to include the well-known optical techniques such as signal mapping imaging (SMI) with the use of a lock-in amplifier in the signal chain and e-beam device perturbation. This paper highlights some of the achievements from an Intel in-house built e-beam tool on current technology nodes. The discussion covers the demonstration of fin and contact resolution on the current technology nodes by EBP and the analysis of the SRAM array with EBP and EBP of metal lines. By utilizing EBP, it has been demonstrated that logic state imaging, SMI, and waveform have significantly improved spatial resolution compared to the current optical fault isolation analogues.

Laser scanning microscope (LSM) based waveform acquisition is widely used in advanced CMOS IC design validation and debug application. Complex waveforms obtained from LSM probing on CMOS ICs are often difficult to fully comprehend without deep understanding of the complex physics involved even in planar CMOS. The introduction of 3-D Tri-Gate transistors since 2010 made this even more challenging. In this paper, we present both model based simulation and probing validations on the most advanced 3D Tri-Gate based CMOS ICs that give us a clear understanding of the nature of these complex waveforms.

A novel fault isolation technique, electron beam induced resistance change (EBIRCh), allows for the direct stimulation and localization of eBeam current sensitive defects with resolution of approximately 100nm square, continuing a history of beam based failure isolation methods. EBIRCh has been shown to work over a range of defects, significantly decreasing the time required for isolation of shorts through straightforward high resolution imagery, allowing for explicit visual defect isolation with a linear resolution of approximately 10nm. This paper discusses the operational setups for the source and amplifier while performing an EBIRCh scan, describes the processes involved in the Intel test vehicle that was used to test EBIRCh, and provides information on two independent functional theories for EBIRCh that operate in conjunction to a greater or lesser extent depending on the defect type. EBIRCh is expected to improve through-put and resolution on various defect types compared to conventional fault isolation techniques.

Logic State Imaging (LSI) using Infra-Red Emission Microscopy (IREM) [1-4] has been an indispensable technology for silicon CMOS process development and product debug applications. Its main limitations are relatively poor spatial resolution due to the broadband near-infrared photons emitted, and poor Signal to Noise Ratio (SNR) with low voltage and low leakage processes and products. Continuous-Wave Laser Scanning Microscope (CW-LSM) based Signal Imaging and Probing (CW-SIP) [5-9] technology is also widely used. It features inherently better spatial resolution than IREM, due to the use of monochromatic 1319nm or 1064nm laser light, and high SNR due to its weaker dependence on voltage and leakage, and, for signal imaging applications, the use of narrow band detection to reduce noise. However, CW-SIP can only detect modulating signals, so it couldn’t previously be applied to LSI. In this paper, we introduce an innovative approach that overcomes this limitation to enable Laser Logic State Imaging (LLSI). Actual fault isolation and design debug cases using this technology are presented to show its advantages in terms of resolution (>50% better), SNR (>2X better) and throughput time improvement, especially at low voltages (down to 500mV).