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1-17 of 17
Ted Lundquist
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Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 214-218, November 15–19, 2020,
Abstract
View Papertitled, Electrical Probing of 7nm SRAMS/SOC at Contact Layer
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for content titled, Electrical Probing of 7nm SRAMS/SOC at Contact Layer
For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 192-196, November 10–14, 2019,
Abstract
View Papertitled, Comparison of He + and Ga + Voltage Contrast in N-wells
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for content titled, Comparison of He + and Ga + Voltage Contrast in N-wells
The examination of partially deprocessed ICs for well imaging has been investigated. First it has been shown [1] that Ga+ FIB imaging can readily and strongly highlight the N-well / P-well boundary in an IC as shown again here. Second, a model which only considers secondary electron creation and scattering [2] is confirmed to be sufficient for understanding these imaging effects. Heavy Ga doping provides no marked change in PVC (passive voltage contrast). Then comparisons in the same field of view between optimized He+ and Ga+ imaging, has shown that He+ provides much greater PVC contrast when looking through deep oxide, and much better resolution on shallow surfaces. The quantitative model Stopping and Range of Ions in Matter (SRIM) [3] was consulted and confirmed these expectations for resolution and depth superiority of the He+ beam. According to the SRIM, there may even be less damage from the He+ beam. Yet these known effects of Ga+ damage has not prevented its widespread use in semiconductor FA and process monitoring. Thus, the use of GFIS (Gas field ion source) He+ beam for voltage contrast and junction imaging warrants further exploration.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2015) 17 (1): 53–55.
Published: 01 February 2015
Abstract
View articletitled, Evolution of FA Innovation as Revealed by ISTFA's Best Papers
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for article titled, Evolution of FA Innovation as Revealed by ISTFA's Best Papers
This column identifies promising new failure analysis technologies based on the papers published in recent ISTFA conferences. The purpose of the column is not to select the "best of the best," but rather to understand the technologies that have been developed and adopted to solve the ever-growing challenges in failure analysis.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 6-11, November 9–13, 2014,
Abstract
View Papertitled, Novel NIR Camera with Extended Sensitivity and Low Noise for Photon Emission Microscopy of VLSI Circuits
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for content titled, Novel NIR Camera with Extended Sensitivity and Low Noise for Photon Emission Microscopy of VLSI Circuits
This work presents a new photon emission microscopy camera prototype for the acquisition of intrinsic light emitted from VLSI circuits during their normal operation. This novel camera was designed to be sensitive to longer wavelengths in order to maximize the signal intensities from modern VLSI chips which are characterized by a red shift in the intrinsic emission spectrum. In this paper, we will characterize the performance of the camera using 32 nm and 22 nm SOI chips. The novel camera is able to collect emission images with the circuit under test operating at a supply voltage down to 0.5 V, exceeding the performance of a state-of-the-art InGaAs camera.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 335-339, November 9–13, 2014,
Abstract
View Papertitled, Continuous-Wave 1064 nm Laser for Laser Voltage Imaging and Probing Applications
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for content titled, Continuous-Wave 1064 nm Laser for Laser Voltage Imaging and Probing Applications
Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 406-412, November 9–13, 2014,
Abstract
View Papertitled, Ultra-Low Voltage Time-Resolved Emission Measurements from 32 nm SOI CMOS Integrated Circuits
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for content titled, Ultra-Low Voltage Time-Resolved Emission Measurements from 32 nm SOI CMOS Integrated Circuits
This work presents a comparison of two generations of Superconducting nanowire Single-Photon Detector (SnSPD) prototypes used for Time-Resolved Emission (TRE) measurements from VLSI chips. The performance of the systems is compared in order to understand the figures of merit that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for ultra-low voltage applications. We will show that measurements down to a new World record low 0.4 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform SNR.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 182-188, November 3–7, 2013,
Abstract
View Papertitled, A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits
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for content titled, A Superconducting Nanowire Single-Photon Detector (SnSPD) System for Ultra Low Voltage Time-Resolved Emission (TRE) Measurements of VLSI Circuits
In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 128-134, November 11–15, 2012,
Abstract
View Papertitled, Near-Infrared Photon Emission Spectroscopy Trends in Scaled SOI Technologies
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for content titled, Near-Infrared Photon Emission Spectroscopy Trends in Scaled SOI Technologies
In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2011) 13 (3): 12–16.
Published: 01 August 2011
Abstract
View articletitled, Laser Voltage Imaging: Setting a New Baseline for Circuit Analysis
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for article titled, Laser Voltage Imaging: Setting a New Baseline for Circuit Analysis
Laser voltage imaging (LVI) enables the global visualization of on-chip circuit activity for the purpose of localizing defects. In a manner reminiscent of e-beam voltage contrast, it allows analysts to visually trace signals through circuit logic in order to see where faults occur. This article explains how laser voltage imaging works and how it is being used in semiconductor failure analysis. It also describes the types of applications for which LVI is not well suited.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2011) 13 (2): 12–18.
Published: 01 May 2011
Abstract
View articletitled, The Copper Challenge to Circuit Edit
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for article titled, The Copper Challenge to Circuit Edit
The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 5-13, November 14–18, 2010,
Abstract
View Papertitled, Laser Voltage Imaging: A New Perspective of Laser Voltage Probing
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for content titled, Laser Voltage Imaging: A New Perspective of Laser Voltage Probing
Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 426-430, November 14–18, 2010,
Abstract
View Papertitled, Pulsed Spot Milling and Deposition to Enable Next Generation Circuit Edit Via Development
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for content titled, Pulsed Spot Milling and Deposition to Enable Next Generation Circuit Edit Via Development
Pulsed spot milling (PSM) and deposition (PSD) extends gallium ion beam technology for circuit edit. Similar to continuous spot mill, a single-point ion beam defines the basic milling profile, however, PSM utilizes a high-speed beam blanker to “pulse” the ion beam. This beam modulation replaces beam rastering by introducing a delay time which is fundamentally equivalent to refresh time during a typical scan pattern to enable and manage chemistry adsorption. Vias with a base diameter <50nm have been enabled by PSM in combination with advanced ion column designs, beam control parameters and endpointing techniques.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 21-26, November 15–19, 2009,
Abstract
View Papertitled, Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform
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for content titled, Extended Circuit Edit, Analysis and Trimming Capabilities Based on the Backside Focused Ion Beam Created Ultra Thin Silicon Platform
Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2009) 11 (3): 46–47.
Published: 01 August 2009
Abstract
View articletitled, Delivering Value
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for article titled, Delivering Value
At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2008) 10 (3): 6–16.
Published: 01 August 2008
Abstract
View articletitled, Can FIB Circuit Edit Successfully Address Interconnect Trends?
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for article titled, Can FIB Circuit Edit Successfully Address Interconnect Trends?
FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.
Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2007) 9 (4): 6–13.
Published: 01 November 2007
Abstract
View articletitled, E-Beam Probing: An IC Design Debug Success Story
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for article titled, E-Beam Probing: An IC Design Debug Success Story
By providing timing information and throughput as device complexities and operating frequencies were rapidly increasing, the e-beam prober, which integrated CAD navigation and waveform measurements while enabling the user to almost disregard the technology “under the hood,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described.
Proceedings Papers
ISTFA2003, ISTFA 2003: Conference Proceedings from the 29th International Symposium for Testing and Failure Analysis, 45-54, November 2–6, 2003,
Abstract
View Papertitled, IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling
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for content titled, IC Diagnostic with Time Resolved Photon Emission and CAD Auto-Channeling
The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.