For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

The examination of partially deprocessed ICs for well imaging has been investigated. First it has been shown [1] that Ga+ FIB imaging can readily and strongly highlight the N-well / P-well boundary in an IC as shown again here. Second, a model which only considers secondary electron creation and scattering [2] is confirmed to be sufficient for understanding these imaging effects. Heavy Ga doping provides no marked change in PVC (passive voltage contrast). Then comparisons in the same field of view between optimized He+ and Ga+ imaging, has shown that He+ provides much greater PVC contrast when looking through deep oxide, and much better resolution on shallow surfaces. The quantitative model Stopping and Range of Ions in Matter (SRIM) [3] was consulted and confirmed these expectations for resolution and depth superiority of the He+ beam. According to the SRIM, there may even be less damage from the He+ beam. Yet these known effects of Ga+ damage has not prevented its widespread use in semiconductor FA and process monitoring. Thus, the use of GFIS (Gas field ion source) He+ beam for voltage contrast and junction imaging warrants further exploration.

This work presents a new photon emission microscopy camera prototype for the acquisition of intrinsic light emitted from VLSI circuits during their normal operation. This novel camera was designed to be sensitive to longer wavelengths in order to maximize the signal intensities from modern VLSI chips which are characterized by a red shift in the intrinsic emission spectrum. In this paper, we will characterize the performance of the camera using 32 nm and 22 nm SOI chips. The novel camera is able to collect emission images with the circuit under test operating at a supply voltage down to 0.5 V, exceeding the performance of a state-of-the-art InGaAs camera.

Laser-voltage probing (LVP) and imaging (LVI) using a continuous-wave (CW) 1320-1340nm laser have become mainstream techniques for electrical fault isolation. A 1064nm laser with a 20% shorter wavelength offers immediate resolution advantages compared to 1320nm at a cost of increased intrusion. This paper explores the potential of CW 1064nm laser and identifies opportunities in fault isolation

This work presents a comparison of two generations of Superconducting nanowire Single-Photon Detector (SnSPD) prototypes used for Time-Resolved Emission (TRE) measurements from VLSI chips. The performance of the systems is compared in order to understand the figures of merit that a single-photon detector should have to enable the acquisition of time resolved emission waveforms for ultra-low voltage applications. We will show that measurements down to a new World record low 0.4 V supply voltage were made possible by a careful optimization of the detector front-end electronics. We also characterized the emission from devices with different threshold voltages in order to understand how the emission contributions depend on this parameter and how this affects the resulting waveform SNR.

In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.

In this paper, near-infrared photon emission spectroscopy measurements from ring oscillators in 45 nm and 32 nm SOI process technology are compared. Employing a cryogenically cooled camera, the measurements cover a broad spectral range from 1200-2200 nm. Both leakage and switching emission, increase monotonically with the wavelength, suggesting measurements should be made at longer wavelengths than has historically been practiced. The paper discusses the optimum cut-off wavelength for maximum signal-to-noise ratio and the obvious importance of reduced ambient temperature for performing measurements.

Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Pulsed spot milling (PSM) and deposition (PSD) extends gallium ion beam technology for circuit edit. Similar to continuous spot mill, a single-point ion beam defines the basic milling profile, however, PSM utilizes a high-speed beam blanker to “pulse” the ion beam. This beam modulation replaces beam rastering by introducing a delay time which is fundamentally equivalent to refresh time during a typical scan pattern to enable and manage chemistry adsorption. Vias with a base diameter <50nm have been enabled by PSM in combination with advanced ion column designs, beam control parameters and endpointing techniques.

Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.

The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.