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Tan Sze Yee
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 196-200, October 30–November 3, 2022,
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Nowadays, semiconductor components are widely used in home electronic appliances, vehicles, industrial motor controls and beyond. The performance and reliability of these components are becoming more crucial and critical. Generally, a semiconductor component consists of lead frames, wires, dies and die attaches. Within the die, the die backside metallization, also known as “BSM,” plays an important role in electronic component manufacturing. The BSM is a layer that promotes good adhesion, electrical properties and long-term stability as a conductive pathway to the circuits. As such, the inspection on BSM is needed to ensure robustness. Several conventional methods have been developed to analyze the die backside metallization. In this paper, we will discuss the inspection on backside metallization and comparison among five sample preparation methods: mechanical cross section with ion milling, mechanical cross section with FIB cleaning, die frontside decapsulation with FIB cut from die surface and FIB cut from die sidewall, and component frontside lapping with FIB from the remaining silicon. Result comparison will be discussed in case studies and the advantages and disadvantages of the five methods will be compared.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 392-395, October 30–November 3, 2022,
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Copper (Cu) material was extensively studied in the past years and widely implemented in high volume wire bonding process as a replacement of Gold (Au) material during semiconductor device fabrication. No doubt, Cu wire provide low cost alternative to gold with higher thermal and electrical conductivity, but it does pose some drawback especially after reliability stress. One of the most common problem was ball lifted after component gone through several reliability stress tests. In this paper, several FA analytical techniques and procedures will be discussed in detail to demonstrate the use of these techniques in ball lifting investigation.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 429-436, October 28–November 1, 2018,
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Advanced package technology often includes multi-chips in one package to accommodate the technology demand on size & functionality. Die tilting leads to poor device performance for all kinds of multi-chip packages such as chip by chip (CbC), chip on chip (CoC), and the package with both CbC and CoC. Traditional die tilting measured by optical microscopy and scanning electron microscopy has capability issue due to wave or electron beam blocking at area of interest by electronic components nearby. In this paper, the feasibility of using profilemeter to investigate die tilting in single and multi-chips is demonstrated. Our results validate that the profilemeter is the most profound metrology for die tilting analysis especially on multi-chip packages, and can achieve an accuracy of <2μm comparable to SEM.