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Tahir Malik
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Journal Articles
Journal: EDFA Technical Articles
EDFA Technical Articles (2011) 13 (2): 12–18.
Published: 01 May 2011
Abstract
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The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 426-430, November 14–18, 2010,
Abstract
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Pulsed spot milling (PSM) and deposition (PSD) extends gallium ion beam technology for circuit edit. Similar to continuous spot mill, a single-point ion beam defines the basic milling profile, however, PSM utilizes a high-speed beam blanker to “pulse” the ion beam. This beam modulation replaces beam rastering by introducing a delay time which is fundamentally equivalent to refresh time during a typical scan pattern to enable and manage chemistry adsorption. Vias with a base diameter <50nm have been enabled by PSM in combination with advanced ion column designs, beam control parameters and endpointing techniques.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 431-439, November 14–18, 2010,
Abstract
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Focused Ion Beam (FIB) circuit edit (CE) has been playing a pivotal role in providing insight to ramp-up yield. Numerous IC fabrication processes inherently pose unique challenges to FIB circuit edit approaches. Copper (Cu) has been the material of choice for interconnects as technology features shrink to the 180 nm node and below. Thick copper planes are used for multiple reasons that are mentioned later. Milling through thick copper planes has been tremendously challenging and time consuming during FIB circuit edits. Proposed is a methodology to enhance the bulk Cu removal process at astounding etching rates while maintaining planarity.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 110-118, November 15–19, 2009,
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For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.
Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 151-156, November 2–6, 2008,
Abstract
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Circuit Edit (CE) through a conductor requires an insulator to isolate the connection transiting the conductor. We investigate several recipes to determine not just the optimum recipe but also the latitude to provide a means of throughput optimization for a given edit requirement. The results show that trade-offs in deposition rate, robustness and isolation quality can be made to enable this throughput optimization.