By inducing two-photon absorption within the active layer of a 28nm test chip, we demonstrate nonlinear laser-assisted device alteration and single-event upsets by temporarily perturbing the timing characteristics of sensitive transistors. Individual qualitative and quantitative evaluations are presented for both techniques, with lateral resolutions demonstrated with sub-100nm performance. A simplistic signal response rate comparison analysis of these two technologies is also presented.

Innovations in semiconductor fabrication processes have driven process shrinks partly to fulfill the need for low power, system-on-chip (SOC) devices. As the process is innovated, it influences the related design debug and failure analysis which have gone through many changes. Historically for signal probing, engineers analyzed signals from metal layers by using e-beam probing methods [1]. But due to the increased number of metal layers and the introduction of flip chip packages, new signal probing systems were developed which used time resolved photon emission (TRE) to measure signals through the backside. However, as the fabrication process technology continues to shrink, the operating voltage drops as well. When the operating voltage drops below 1.0V, signal probing systems using TRE find it harder to detect the signals [2]. Fortunately, Laser Voltage Probing (LVP) technology [3] is capable of probing beyond this limitation of TRE. In this paper, we used an LVP system to analyze and identify a functional shmoo hole failure. We also proposed the design change to prevent its reoccurrence.

Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Novel Fabry Perot [1] fringe analysis techniques for monitoring the etching process with a coaxial photon-ion column [2] in the Credence OptiFIB are reported. Presently the primary application of these techniques in circuit edit is in trenching either from the front side or from the backside of a device. Optical fringes are observed in reflection geometry through the imaging system when the trench floor is thin and semi-transparent. The observed fringes result from optical interference in the etalon formed between the trench floor (Si in the case of backside trenching) and the circuitry layer beyond the trench floor. In-situ real-time thickness measurements and slope correction techniques are proposed that improve endpoint detection and control planarity of the trench floor. For successful through silicon edits, reliable endpoint detection and co-planarity of a local trench is important. Reliable endpoint detection prevents milling through bulk silicon and damaging active circuitry. Uneven trench floor thickness results in premature endpoint detection with sufficient thickness remaining in only part of the trench area. Good co-planarity of the trench floor also minimizes variability in the aspect ratios of the edit holes, hence increasing success rates in circuit edit.

Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.

The latest IC modification requirement is to decrease the resistivity of Focused Ion Beam (FIB) deposits, especially deposits within a FIB machined hole. The resistivity of platinum conductor deposited by FIB within a hole is much greater (5000-50000 μΩ-cm) than that deposited on a surface (~200 μΩ-cm) (1). Auger analysis of surface deposited platinum conductor gives the composition ratios as ~ 50% platinum, ~34% carbon, ~15% gallium and ~1 % Oxygen. The escape solid angle of the organic carrier is much less from a hole than from a surface; therefore, we find more of the non-conductive organic material is trapped inside the hole which increases the fill resistivity. With its planarization and multiple metal levels, advanced IC process technology forces contact to lower level metal to be through high aspect ratio holes. To make a low resistance contact through such a hole, deposited material must have a high ratio of platinum to carbon and Oxygen. An improved technique is needed to remove the organic carrier molecules and deposit material containing this higher platinum percentage. The way to achieve such deposition is to adjust gas arrival rate and beam current to produce a deposition rate that allows sufficient time for the organic carrier molecules to escape. Using this method, we can to obtain fill resistivity of about 1000-2500 μΩ-cm within high aspect ratio holes. This paper discusses in detail the technique to achieve such low resistivity in high aspect ratio holes. On the surface where space is not so limited, a greater deposition rate yields shorter times to resistance as well as better step coverage, but within a hole a lower resistivity material is needed to result in good conductance to lower level metal.