Magnetic field imaging is a well-known technique which gives the possibility to study the internal activity of electronic components in a contactless and non-invasive way. Additional data processing can convert the magnetic field image into a current path and give the possibility to identify current flow anomalies in electronic devices. This technique can be applied at board level or device level and is particularly suitable for the failure analysis of complex packages (stacked device & 3D packaging). This approach can be combined with thermal imaging, X-ray observation and other failure analysis tool. This paper will present two different techniques which give the possibility to measure the magnetic field in two dimensions over an active device. Same device and same level of current is used for the two techniques to give the possibility to compare the performance.

Evaluation techniques for semiconductor devices are keys for device development with low cost and short time to market. Especially, dopant and depletion layer distribution in devices is a critical electrical property that needs to be evaluated. Super-higher-order nonlinear dielectric microscopy (SHOSNDM) is one of the promising techniques for semiconductor device evaluation. We developed a method for imaging detailed dopant distribution and depletion layers in semiconductor devices using SHO-SNDM. As a demonstration, a cross-section of a SiC power semiconductor device was measured by this method and detailed dopant distribution and depletion layer distributions were imaged.

Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.

Adhesive strength of the plasma-sprayed thermal barrier coating (TBC) is one of the most important parameters which influence the reliability during service. In the past, numerous test methods were reported to measure the coating adhesion. However, most of them require careful and time consuming preparation. Consequently, limited information could be obtained to establish the relationship between the processing conditions and the adhesive property. To produce more measurements using a simpler procedure, the interfacial indentation test and the modified tensile adhesive test are examined. In this paper, the interfacial fracture toughness of the plasma-sprayed ZrO 2 coatings, deposited on Al substrates, were evaluated by these two tests. In order to study the effects of the powder injection, samples were sprayed with various carrier gas flow rates. The test results show a certain correlation between the melting index and the interfacial fracture toughness. In addition, variations between the results obtained from the two different methods are discussed.

The microstructure of thermally sprayed ceramic coatings is characterized by the existence of various pores and microcracks. The porous microstructure makes coating desirable for thermal insulation, but this unique microstructural feature also gives rise to anelastic response under tension and compression loads. Detail investigations of curvature measurements of ceramic coated substrate indicate the coatings to exhibit anelastic behavior composed of nonlinear and hysteresis characteristics. In this paper, the mechanisms of such behaviors were studied from curvature-temperature measurements and finite element analysis through modeling the microstructure of yttria stabilized zirconia (YSZ) coating. Computational models contain numerous randomly distributed pores and microcracks with various sizes, aspect ratios, locations and orientations. The effects of such attributes of pores and microcracks on coating anelastic behavior were studied by simulations of curvature change during thermal cycles.

Over the last decade there has been an explosion in terms of available tools for sensing the particle spray stream during thermal spray processes. This has led to considerable enhancement in our understanding of process reproducibility and process reliability. However, in spite of these advances, the linkage to coating properties has continued to be an enigma. This is partially due to the complex nature of the build-up process and the associated issues with measuring properties of these complex coatings. In this paper, we present an integrated strategy, one that combines process sensing, with process modeling and extracting coating properties in situ through the development of robust and advanced curvature based techniques. These techniques allow estimation of coating modulus, residual stress and non-linear response of thermal sprayed ceramic coatings all within minutes of the deposition process. Finally, the integrated strategy examines the role of process maps for control of the spray stream as well as design of thermal spray coatings. Examples of such studies for both MCrAlY and YSZ coatings will be presented.

Locating fault origins of defective logic LSls requires expensive equipment, such as electron beam testers and LSI testers. In order to maximize the utilization of such equipment in achieving high fault analysis throughput as well as to save manpower, the authors are developing an automatic fault tracing system which locates the fault origin overnight without human assistance through control of an electron beam tester and an LSI tester. The system traces backwards via the fault propagation path and locates the fault origin by comparing the behavior of a faulty LSI sample with that of a good LSI sample. Sample exchange in a vacuum chamber is achieved through a dual chip loading mechanism. After initial setting, fault location is accomplished without human assistance by fully automated operations, such as fine tuning SEM images of LSI surfaces, aligning points by robust pattern matching between SEM images and layout data, acquiring voltage contrast images with high contrasts and judging logical voltage levels from the images. A prototype version of this system successfully backtraced to the fault origin of an LSI with 20 k gates in 8 hours.

Pin-point (specific area) planar transmission electron microscopy (TEM) analysis has been improved to study process-induced defects in recent very large scale integrated (VLSI) devices. The specimens are prepared by a combination of marking failure sites with focused ion beam (FTB) equipment and planar TEM specimen preparation technique. This method provides not only planar observation of localized failures with an accurate observation with high positioning accuracy but also wide range of observable area which is feasible to carry out some application techniques associated with TEM. In particular, it is found to be a powerful method to identify the nature of crystalline defects which cause the failures. This work presents the detailed procedure and demonstrates its successful applicability via studying a leaky bipolar transistor in 0.5μm BiCMOS devices (one failure of more than 4500 transistors). The results clarify the presence of stacking faults, formed during epitaxial growth, between collector and emitter regions in the specific transistor with resistive collector-emitter leakage current.