The ICCDLAB (Integrated Circuit for Characterization and Debug Laboratory) test chip is a full custom silicon chip dedicated to failure analysis. This chip embeds several custom devices designed to highlight, reproduce, and simulate defects, as well as enhance the signatures obtained through failure analysis techniques that are used to locate defects in circuits. The ICCDLAB serves as a versatile tool for failure analysts, providing a “Swiss army knife” and a failure analysts’ playground at the same time. The chip offers a simple means of covering an exhaustive catalog of failure analysis techniques and approaches, allowing for equipment benchmarking, training of individuals new to the failure analysis field, understanding of failure mechanisms and signatures, simulation of defect behaviors, and support for development of new techniques.

Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).

This paper presents a study about the invasiveness of 1340 nm continuous wave laser used for electrical failure analysis on 28 nm advanced technologies. It underlines the potential laser-induced degradation for deep submicron technologies that could jeopardize analysis results by modifying physical and chemical properties at substructure level. The impact of laser power on transistor morphology and electrical behavior is studied and the results of this study enable us to setup safe experimental conditions.

By adding a transmission grating into the optical path of our photon emission system and after calibration, we have completed several failure analysis case studies. In some cases, additional information on the emission sites is provided, as well as understanding of the behavior of transistors that are associated to the fail site. The main application of the setup is used for finding and differentiating easily related emission spots without advance knowledge in light emission mechanisms in integrated circuits.

The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.

In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.

The bridge defect is one of the most difficult defects to locate. When classical static and dynamic optical techniques reach their limits, applying a dynamic signal on the power supplies for stimulating the defect allows obtaining useful additional information helping the localization. In this paper, we explore these techniques on a real case analysis of bridge defect in a scan chain on a 28nm technology node circuit. We will show that OBIRCH, LVI, static & dynamic EMMI do not give significant signatures for the defect localization. Finally we show that EMMI and LVI signatures applying a clock on the power supply bring relevant information to locate efficiently the defect.

For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.