As technology continues to scale down, semiconductor devices and circuitry have become more complex. The layouts are more integrated and the devices do not isolate at contact level like they used to. Due to this, nanoprobing cannot always localize the defect to one gate finger and as a result the follow-on physical analysis gets more complicated and time consuming. In this paper, we will explore an approach to simplify a given circuit and localize the failing finger in that circuit by cutting metal lines using diamond nano-probes [1] on the FEI Hyperion Atomic Force Probe (AFP) Platform. We will also describe some of the other applications of diamond nano-probes in facilitating semiconductor failure analysis.

Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

As semiconductor technology keeps scaling down, the conventional physical failure analysis processes have faced increasing challenges and encountered low success rate. It is not only because the defect causing a failure becomes tinier and tinier, but also because some of these defects themselves are invisible. Electrical nano-probing with narrowing down a defect to a single transistor has greatly increased the likeliness of finding a tiny defect in subsequent TEM (transmission Electron Microscope) analysis. However, there is still an increasing trend of encountering an invisible defect at most advanced technology nodes. This paper will present how to identify the root causes of three such invisible defects with the combination of electrical nano-probing and TEM chemical analysis.

This paper describes novel concepts in equipment and measurement techniques that integrate optical electrical microscopy and scanning probe microscopy (SPM) capabilities into a single tool under the umbrella of optical nanoprobe electrical (ONE) microscopy. Optical imaging ONE microscopy permits non-destructive measurement capability that was lost more than a decade ago, when the early metal levels became electrically inaccessible to microprobers. SPM imaging techniques do not have sensitivity to many types of defects, and nanoprobing all of the transistors in an area pinpointed by optical electrical microscopy is often impractical. Thus, in many cases, ONE microscopy capability will permit analytical success instead of failure.

Resistive gate defects are unusual and difficult to detect with conventional techniques [1] especially on advanced devices manufactured with deep submicron SOI technologies. An advanced localization technique such as Scanning Capacitance Imaging is essential for localizing these defects, which can be followed by DC probing, dC/dV, CV (Capacitance-Voltage) measurements to completely characterize the defect. This paper presents a case study demonstrating this work flow of characterization techniques.

The laboratory practice of employing atomic force probing (AFP) using AFP current imaging and Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for identfication of front end of line (FEOL) defects in MOSFET devices, especially for silicon on insulator applications has been extensively detailed [1,2,3]. The introduction of Nanoprobe Capacitance Voltage Spectroscopy (NCVS) on bulk silicon wafers and silicon on insulator (SOI) wafers to characterize discrete MOSFET and SOI embedded dynamic ramdom access memory devices (eDRAM) without the time consuming delayering methods of conventional scanning capacitance microscopy has also been highlighted [1,2,3,4,5,6]. Typically, this laboratory AFP characterization is employed on die fragments sampled from whole wafers following back end of the line (BEOL) metallization processing and test. The process vintage of this hardware can be as much as three months after the critical FEOL processing has occurred. This paper is intended to describe for the first time the methodology of applying AFP on whole 300mm wafers at the post CA chemical-mechanical polishing (CMP) process level to provide a real time insight into yield issues that would not be detected until subsequent BEOL metallization processing and testing. This new AFP tool incorporates enhanced features enabling both DC measurements as well as AC capacitance voltage measurements of discrete deep trench embedded DRAM (eDRAM) devices for 32nm, 28nm, and 20nm node technologies.

Root cause analysis of frequency sensitive “soft” failures in SRAM arrays pose unusual challenges to the failure analyst. Conventional atomic force probe (AFP) DC measurements cannot reliably identify the failure source. The employment of tester based schmoo screening have been shown to correlate with AFP AC quantitative capacitance measurements for the first time. The technique of Nanoprobe Capacitance-Voltage Spectroscopy (NCVS) at contact level (CA) for localization has been previously described [1,2,3]. By exploiting the dC/dV component of the NCVS signal shown in Figure 1 and integrating this output, a quantitative capacitance versus voltage measurement can be demonstrated. This quantitative capacitance measurement identified a frequency sensitve horizontal pair failure (HPF) in the SRAM array. Subsequent process vintage analysis identified the source and eliminated these frequency sensitive HPF characterisics. Given the sensitive nature of these fails, conventional physical analysis methods of TEM EELS, and cross section scanning capacitance analysis were not successful in finding the root cause. This underlies a paradigm shift in failure analysis. Electrical measurements may be the only means to identify a process problem and follow-up process vintage analysis is required to solution the root cause.