A successful failure analysis not only depends on extensive electrical and physical fault isolation by using all the advanced FA tools to narrow down the possible failure site, but also relies on actual physical defect findings. For advanced IC devices with technologies approaching sub-10nm and more than 10 layers of metallization built in ultra-low k materials, finding convincing physical defects becomes increasingly challenging. Backside deprocessing to reveal the physical defects at the active circuit layers and interconnect layers have been mostly done with KOH or TMAH as bulk Si etching chemicals, and some successful results have been published in the literatures. However, some challenges are also reported using these chemicals to achieve satisfactory results. In this paper, an improved backside deprocessing technique will be discussed using a special bulk Si etching chemical, choline hydroxide, to successfully reveal the physical defects on advanced IC devices. The new technique showed advantages over the existing techniques with more predictable and reliable results for backside deprocessing work. Two case studies will also be shared to demonstrate how this improved technique has been utilized to successfully reveal the physical damage at transistor gate level on the advanced MCU devices.

In this work we present a new defect localization capability on Wafer Level Chip Scale Packages (WLCSP) with small-scale Cu pillars using advanced 3D X-ray microscopy (XRM). In comparison to conventional microcomputed tomography (Micro-CT or microCT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Two case studies on actual failures (one from the assembly process and one from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis (FA) process by locating the defects non-destructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis.

Current VLSI devices have very complicated circuit designs and very small feature size. As a result, fault isolation on failing devices becomes a more and more challenging task. Although backside photoemission technique is commonly used to detect the failure site covered with multiple metal layers, it has the disadvantages of more time consumption and less success rate. Without a localized failure site, it will be very difficult, sometime even impossible, to find the physical evidence for the failures. This article describes a method that has been successfully used for isolating the wordline leakage on a memory FLASH device using FIB cutting and passive voltage contrast on the leaky wordline. The concept of this article is not just limited to this application; rather it can be used for all similar types of fault isolation work for other applications.