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1-4 of 4
Sungsoo Yim
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 362-364, October 30–November 3, 2022,
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DRAM is a type of memory that stores each bit of data in a capacitor cell, leakage current is a very important electrical parameter to retain data. Therefore, larger cell capacitance and smaller leakage current have been regarded as key factors in continuous shrinkage of DRAM. Generally, gate induced drain leakage (GIDL) and junction leakage of cell transistor (CTR) are well-known, but our approach is focused on retention failure by bulk trap. In order to electrically observe the influence of bulk trap, we used the adjacent gate of CTR to control electron migration. Results show that there are many failure cells due to bulk trap, and dimension shrinkage accelerates this failure. Consequently, balancing among electrical bias point and transistor manufacturing process should be carefully considered with bulk traps.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 263-268, October 31–November 4, 2021,
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There are many wafer level tests, such as Fail Bit Count (FBC), where conventional statistical analysis methods are inadequate because the associated data do not follow a normal distribution. This paper introduces a statistical failure analysis technique that does not rely on location and scale parameters and is thus able to handle such cases. It describes the math on which the method is based and explains how to determine effect size (ES) using the quantile comparison equivalence criteria (QCEC) and a statistical parameter, called the center of dispersion (CoD), that distinguishes between center difference and dispersion difference. It also includes a case study showing how the new method is used to assess the effect of a process change on dynamic random access memory test data and how it compares in terms of accuracy with conventional statistical techniques.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 264-266, November 15–19, 2020,
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As scaling-down of dynamic random access memory (DRAM) has been continued, the pitch of metal-line already reached sub-50nm where it is hard to define the soft bridge and normal one. Moreover, the metal bridge failure at system level cannot be corrected with in-situ system error-code correction (ECC) modules. In order to screen these failures in the wafer or/and package level electrical tests, high voltage stress methods are necessary. Therefore, accurate stress quantity decided by combination temperature, voltage and time, and effective stress methodologies are essential for high quality and reliability. For a mass production environment, a wafer level burn-in (WBI) can enable multiple word-lines simultaneously and consistently is appropriate. Moreover, we confirmed the actual voltage level on real cells in WBI and optimized stress parameters in terms of time and voltage. Finally, it was proven through the WBI evaluation for over 60k DRAM chips.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 277-279, November 15–19, 2020,
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As dimension shrinkage, uncommon phenomena have been occurring during write and read operation in DRAM. These phenomena are strongly related cell capacitance, and the sensitivity of leakage current increases. Leakage current, especially in cell capacitor or cell transistor, is a major cause of the imbalance between stored charge in write operation and served charge in the read operation. Generally, error induced by leakage current appears data-1 failure, but in our study data-0 failure is observed in the case of extreme low cell capacitance that failure level is ppb (parts per billion). Results show that this phenomenon is influenced by cell capacitance, gate/body voltage of cell transistor, and supplied voltage level of the bitline sense amplifier. Based on various results, the electron loss to form inversion electron channel of cell transistor is regarded as a major factor like Charge Feedthrough [5].