Presentation slides for the ISTFA 2024 Tutorial session “An Introduction to the FIB as a Microchip Circuit Edit Tool (2024 Update).”

Presentation slides for the ISTFA 2024 Tutorial session “Fundamental Considerations in the Justification, Design and Construction of an Analytical Laboratory for High Tech Imaging and Processing Tools (2024 Update).”

Presentation slides for the ISTFA 2023 Tutorial session “An Introduction to the FIB as a Microchip Circuit Edit Tool (2023 Update).”

This presentation introduces the practice of focused ion beam (FIB) chip editing and its power and versatility as a problem-solving tool. It begins with a review of the features and functions of FIB systems, the role of gas chemistry in milling, etching, and deposition, and the use of IR imaging for navigation and targeting. It goes on to identify challenges due to packaging materials, chip-package interactions, and other factors, and in each case, provide alternate approaches and procedures to circumvent potential problems. It also covers advanced practices and methods and assesses potential future advancements.

This presentation introduces the practice of focused ion beam (FIB) chip editing and its power and versatility as a problem-solving tool. It begins with a review of the features and functions of FIB systems, the role of gas chemistry in milling, etching, and deposition, and the use of IR imaging for navigation and targeting. It goes on to identify challenges due to packaging materials, chip-package interactions, and other factors, and in each case, provide alternate approaches and procedures to circumvent potential problems. It also covers advanced practices and methods and assesses potential future advancements.

The sample preparation required for a typical backside circuit edit (CE) is a significant barrier for some labs, as it requires specific hardware and considerable operator expertise. There are also instances in which it is not possible to mechanically thin the silicon in the typical fashion. This paper addresses the possibility of backside CE be performed on full-thickness silicon devices and the possibility of skipping off the thinning step, as well as the advantages and disadvantages of this approach. Sample trenches are shown, and trenching optimization experiments are described. The paper addresses the issues of navigation, including IR imaging through full-thickness silicon, and how it depends on the sample doping levels. Finally, it presents data on a novel navigational technique that can be employed to improve targeting accuracy. The paper shows that backside CE on full-thickness silicon devices is possible despite the challenges.

For most advanced semiconductor products, the preferred methodology for achieving Focused Ion Beam (FIB) circuit modification and node access is through the backside of the chip. The high density of interconnect wiring and the presence of C4 solder bumping has made complex edits virtually impossible with conventional frontside techniques. IBM has developed a set of procedures for performing backside edit on circuits built using the Silicon-On-Insulator (SOI) process. While the basic approach and techniques parallel many of the established practices developed for handling transistors built in conventional bulk silicon, there are a number of key and critical differences. In this paper, we will address the basic instruction set developed for successful FIB work on SOI product. This will include backside silicon surface preparation, charge control, endpointing during high volume silicon removal, global and local coordinate lock techniques, floor voltage contrast phenomena, floor preparation and preservation, fill pattern issues and advantages, and finally the target structure alignment, access, connection and/or removal. Post process bake and handling will also be discussed.

Focused Ion Beam (FIB) success has become more difficult as microchip process technology advances, requiring new techniques for damage control both during the microsurgery procedure and before the finished product can be electrically tested. Ultra thin gate dielectrics, shallower junctions, less ‘white space,’ and new materials surrounding active devices all create additional challenges for imaging, targeting, controlling instantaneous charge damage, and the removal of residual implanted charge. On the macro level, global thinning of bulk silicon housed in hybrid packages is causing new problems with thermal management and mechanical stress. Techniques and procedures used to control electrostatic discharge type damage become ever more critical when working on poorly buffered or isolated device elements, especially from the backside. Implanted gallium and residual charge perturb electrical characteristics, and must be dispersed prior to power-up thru carefully controlled bake steps. Left in place, these FIB-induced perturbations are likely to cause poor functionality or even latchup. The mechanical rigidity and thermal dissipation properties of newer, complex package types must also be restored post-FIB, otherwise cracked silicon or a thermal overload event might be the outcome. In this paper, we will attempt to address some of the common causes of FIB-induced failure on newer silicon and package technologies, and how they might be overcome. FIB techniques and preparatory processes must continue to evolve in order to deal effectively with the problems of direct beam damage, residual charge elimination, and sample stress management.