This paper presents a systematic approach of failure analysis to determine the source of electrical overstress condition to a digital variable gain amplifier (DVGA) module where the failure was due to attenuation accuracy. Having consideration of the physical evidence on the failed devices and the root cause of the failure gives an insight of how the mechanical damage caused an electrical overstress exposure to the devices. The paper provides information on destructive analysis and non-destructive analysis conducted for determining the root cause of the failure of the DVGA module. Analysis revealed that devices failed due to an electrical overstress exposure through mechanical damage to the passivation of the metal-2 lines. The mechanical damage occurred during die-sort testing due to misalignment of the probes which delivered unintended electrical stress to the devices.

A single power amplifier-duplexer device was submitted by a customer for analysis. The device was initially considered passing when tested against the production test. However, further electrical testing suggested that the device was stuck in a single power mode for a particular frequency band at cold temperatures only. This paper outlines the systematic isolation of a parasitic Schottky diode formed by a base contactcollector punch through process defect that pulled down the input of a NOR gate leading to the incorrect logic state. Note that this parasitic Schottky diode is parallel to the basecollector junction. It was observed that the logic failure only manifested at colder temperatures because the base contact only slightly diffused into the collector layer. Since the difference in the turn-on voltages between the base-collector junction and the parasitic Schottky diode increases with decreasing temperature, the effect of the parasitic diode is only noticeable at lower temperatures.

This paper outlines the systematic isolation of an electrostatic discharge defect on a depletion-mode FET. Topics covered are fault isolation, FIB-STEM cross-section and EDS analysis, and defect simulation. Multiple GaAs PA devices were submitted for analysis after failing different reliability stresses. Fault isolation revealed ESD damage on a DFET connected to the VMODE0 pin. Simulation of the failure showed that, most likely, the defect was caused by CDM stress. A design change of inserting a resistor between the VMODE0 pin and the DFET made the device more robust against CDM stress.

This paper outlines the failure analysis of a Radio Frequency only (RF-only) failure on a complex Multimode Multiband Power Amplifier (MMPA) module, where slightly lower gain was observed in one mode of operation. 2 port S-parameter information was collected and utilized to help localize the circuitry causing the issue. A slight DC electrical difference was observed, and simulation was utilized to confirm that difference was causing the observed S-parameters. Physical analysis uncovered a very visible cause for the RF-only failure.

The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.