This paper places a strong emphasis on the importance of applying Systematic Problem Solving approach and use of appropriate FA methods and tools to understand the “real” failure root cause. A case of wafer center cluster RAM fail due to systematic missing Cu was studied. It was through a strong “inquisitive” mindset coupled with deep dive problem solving that lead to uncover the actual root cause of large Cu voids. The missing Cu was due to large Cu void induced by galvanic effects from the faster removal rate during Cu CMP and subsequently resulted in missing Cu. This highlights that the FA analyst’s mission is not simply to find defects but also play a catalyst role in root cause/failure mechanism understanding by providing supporting FA evidence (electrically/ physically) to Fab.

This paper illustrated the beauty of AFP nano-probing as the critical failure analysis tool in localizing new product design weakness. A 40nm case of HTOL Pin Leakage due to Source/Drain punch-through at a systematic location was discussed. The root cause and mechanism was due to VDS overdrive testing issue. This paper placed a strong emphasis on systematic problem solving approach, deep dive and use of right FA approach/tool that are essentially critical to FA analysts in wafer foundry since there is always minimal available data provided. It would serve as a good reference to wafer Fab that encountered such issue.

In this paper, we will describe a low yield case which revealed itself as leakage failures near the wafer edge. A systematic problem solving approach was used based on the application of a variety of FA techniques such as electrical curve tracing, Spreading Resistance Probing (SRP), Secondary Ion Mass Spectrometry (SIMS), and Chemical Analysis coupled with extensive Fab investigations. These techniques transformed an invisible defect into a visible one, leading to a full resolution of the issue with good understanding of the failure mechanism and the root cause. We will show that the wafer edge leakage was the result of N-type contamination of the substrate due to Phosphorus outgassing from the V-ring during the high temperature Argon anneal process.

Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals. Based upon the backside photoemissions detected on the capacitor structures within the PLL block and the ruptures observed at the emission spots on the polysilicon and gate oxide or of the capacitor after physical deprocessing, the failure was proved due to the capacitor gate-oxide breakdown. This was believed to be caused by the plasma-induced-damage during high-density-plasma (HDP) CVD oxide deposition after the front-end processes, as only the lots from one HDP-CVD deposition equipment have very high percentage PLL functional failure. Subsequent machine commonality check did find non-uniform inter layer dielectric (ILD) thickness from this equipment, which indicated the non-uniform plasma intensity occurred during the ILD film deposition. This was further confirmed by the finding of a worn-out gas-shower-head in this system. The abnormal high density of plasma created extra charging and caused the PLL poly capacitor’s gate oxide breakdown due to the antenna effect. After replacing the gas showerhead, the failure disappeared and yield was back to normal. Through this low yield analysis, we demonstrated an effective application of backside photoemission microscopy to fab yield improvement.

The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.