Nanoprobing logic based SOI embedded DRAM cells for on-processor designs poses different challenges than probing conventional six transistor SRAM designs. This paper will describe nanoprobing logic based embedded DRAM (eDRAM) cells in 65nm SOI applications. We will also describe probe placement and measurement methodology for electrical characterization of leakage between deep trench capacitors composing those eDRAM designs. The introduction of nano CV metrology and scanning capacitance imaging for use in characterizing DRAM capacitors will also be discussed.

To reconstruct discrete device threshold characteristics at tungsten contact level with atomic force probe (AFP), specific care in making drive current measurements is essential. Kelvin probing as well as the proper placement of the AFP probes themselves is an absolute requirement for insuring precise measurements. For this paper, NFET and PFET test structures employing 3 micrometer gate widths are used to simulate a sense-amp device. The results obtained using normal pad-level probing on a conventional probe station with results from an AFP nanoprober with and without Kelvin sensing are compared. These measurements are also compared with the nominal or expected design rule values. Experimental results comparing AFP Kelvin measurements at contact level on the same MOSFET test structure versus measurement obtained conventionally at pad level underscores the importance and value of AFP Kelvin measurements.