Novel sample preparation techniques have been developed for Three-Dimensional Heterogeneously Integrated (3DHI) devices to enable precise failure analysis while protecting adjacent components. Traditional grinding and polishing methods risk damaging surrounding areas when tool bits extend beyond the target region. Using the VarioMill system's high-precision stages (±1µm accuracy), we introduce three key innovations: a helical grinding approach for accessing die centers, an extended tool bit technique for processing rectangular corners, and enhanced polishing protocols. These methods allow for targeted sample preparation of individual dies or specific die regions while completely preserving adjacent components. The techniques are particularly valuable for complex, densely packed 3DHI devices where conventional preparation methods pose significant risks of collateral damage.

Advanced node semiconductor reverse engineering has always demanded cutting-edge techniques to cleanly extract the key structural information from the integrated circuit (IC) design. Core circuit edit technologies such as taking a backside wafer approach, employing scanning focused ion beam (FIB) recipes, optimized chemical delivery, and endpoint technology based on ultraviolet (UV) photon spectroscopy can play an important role in success. Once delayered, the IC's structural layers can be subjected to high-resolution scanning electron microscope (SEM) imaging. A new tool has been developed that incorporates these capabilities for dedicated IC delayering. These capabilities allow for the visualization of individual layers, transistors, interconnects, and other critical elements at nanometer-scale resolution, unveiling valuable insights into the IC's design and functionality.

Reproducible laser-assisted metal deposition with copper hexafluoroacetylacetonate trimethylvinylsilane Cu(hfac) (TMVS) has been demonstrated on a range of relevant semiconductor insulating material surfaces including silicon dioxide (SiO 2 ), crystalline silicon (c-Si), and organic package material such as polyimide and printed circuit board (PCB) FR- 4. A key to reliable and chemically efficient growth is a novel copper chemistry delivery methodology using direct precursor pulsing. The laser power conditions for deposition are strongly correlated to the substrate material, with increased power for the more thermally conductive samples (0.8 – 1.0 W) and significantly less for packaging materials (50 mW). The laser-assisted copper growth results and material properties are comparable to the published literature. Examples of circuit modifications using this methodology demonstrate its valuable role in the future of circuit edit.

Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.

The journey to the circuit layer will be described by first discussing baseline processes of laser assisted chemical etching (LACE) steps before the focused ion beam (FIB) workflow. These LACE processes take advantage of a dual 532 nm continuous wave (CW) and pulse laser system, however limitations and overhead that is transferred over to the FIB operator will be demonstrated. Experiments show an additional third 355 nm ultraviolet (UV) pulse laser process introduction into the workflow can further reduce the remaining silicon thickness (RST) relieving FIB overhead. In addition, complex pulse laser patterning techniques will show a refinement to nonuniform produced silicon. Finally, other pulse laser patterning techniques such as polygon etch capability will allow laser etching around and in-between features to enhance circuit layer accessibility for debug operations.

Infrared optical probing techniques that have significant applications to and continued development for silicon physical debug have existed for decades. More recently, resolution enhancement achieved by improving numerical aperture, etc. have reached fundamental limits and the ability for resolution to match node scaling with radiation transparent to silicon (photon energy < silicon bandgap) becomes diffraction limited for some 10nm and many future process nodes. Decreasing the wavelength used for imaging and signal acquisition can improve resolution; however, it is well documented that absorption increases sharply for photons with energy greater than the bandgap of the bulk substrate material. Significant reduction in the thickness of the backside substrate material can be performed to achieve acceptable transmission through the absorbing substrate, but the requirement for very thin sample preparation significantly modifies the thermal system surrounding active circuitry. Here, high aspect ratio trenches are shown to offer a unique method to take advantage of thick silicon (> 100µm) for lateral heat dissipation as well as thin silicon (< 2µm) for minimally absorbing optical path in close proximity to enable case-by-case preparation methods for postsilicon labs faced with visible light resolution requirements on high power density circuits.

This paper discusses the development of an extensible programmatic workflow that leverages evolving technologies in 2D/3D imaging, distributed instrument control, image processing, and automated mechanical/chemical deprocessing technology. Initial studies involve automated backside mechanical ultra-thinning of 65nm node IC processor chips in combination with SEM imaging and X-ray tomography. Areas as large as 800μm x 800μm were deprocessed using gas-assisted plasma FIB delayering. Ongoing work involves enhancing the workflow with “intelligent automation” by bridging FIB-SEM instrument control and near real-time data analysis to establish a computationally guided microscopy suite.

The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.

Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

Visible light laser voltage probing (LVP) for backside improved optical spatial resolution is demonstrated on ultrathinned bulk Si samples. A prototype system for data acquisition, a method to produce ultra-thinned bulk samples as well as LVP signal, imaging, and waveform acquisition are described on bulk Si devices. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require backside sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces will typically use conventional Laser Chemical Etching (LCE) platforms. The focus of this analysis will be to investigate and conjoin previously published techniques to this local preparation by using a combination of laser sources. A Continuous Wave (CW) and Pulse laser will be used at various processing stages to de-process IC packaging materials silicon and mold compound encapsulation.

Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. Ultra-thin RST enables VIS light techniques such as laser voltage probing. In this work we investigate the lower RST limit due to sub-surface damage from grinding and a one-step polishing method to achieve 3 um RST (+/- 0.8 um) over 121 mm2 die (11 x 11 mm) test package as well as 5 um (+/- ) over 109.2 mm2 (8.0 x 13.7mm) active device.

The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.

Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation that etches backside silicon to ultra-thin remaining layer thickness for Focused Ion Beam (FIB) circuit edit and failure analysis of Wafer Level Packages (WLP). PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.

Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.