Presentation slides for the ISTFA 2023 Tutorial session “TEM Techniques for Semiconductor Failure Analysis.”

Presentation slides for the ISTFA 2023 Tutorial session “Advanced FIB/SEM Sample Preparation and Analysis Techniques.”

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.

FA cannot consist of simply jumping to conclusions. The FA process is validated through correlation with the initial failure and through interpretation of the obtained results, subjective by definition. This paper illustrates the difficulty of analyzing complex failures caused by multiple factors, including wafer fabrication, assembly, and application conditions. Inter-Layer Dielectric (ILD) delamination was experienced on various ICs from the same 250nm technology. A complete set of techniques (C-SAM, laser and optical microscopy, SEM, FIB cross-sections, TEM, EFTEM, SIMS, Auger, delineation) was used as different pieces of the same puzzle to reveal the multiple factors contributing to the ILD delamination failures. Due to the subtle nature of some of the underlying causes, defining an accurate FA approach with appropriate sample preparation and accurate device traceability was critical to understanding this complex, multivariate issue.

As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.

This paper outlines the analysis of a flash single bit failure caused by bitcell degradation over write/erase cycling. With no physical anomaly present at the failing single bit, Atomic Force Probing (AFP) characterization was utilized in conjunction with thermal response characterization to direct analysis towards a particular non-visible defect as the root cause. Existence of the hypothesized non-visible defect causing the single bit cycling failure was proven through Transmission Electron Microscopy (TEM) stained sample analysis, which highlighted an anomalous lateral drain junction formation at the single bit that caused the cycling failure.

Advanced technologies with higher gate leakage due to oxide tunneling current enable detection of high resistance faults to gate nodes using a straight forward resistance measurement.

This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.

Passivation damage, a common failure mode in microelectronics circuitry, can be easily identified by optical inspection in the form of a local 'discoloration' after exposing the die to a chemical that would penetrate through the crack and attacks metal lines. Unfortunately, this process destroys evidence of what damaged the passivation, since it attacks the damaged region. As a result, in many cases, the mechanism by which the passivation damage occurred is unclear. This problem is addressed in this paper by a procedure to examine passivation damage by transmission electron microscopy (TEM) of a cross-section sample prepared from the backside and without exposing the die from the top side. The backside approach was successfully used to assign the root cause of the passivation damage to packaging process. A topside approach to characterize the passivation damaged region can result in destruction of evidence at the defect location.

Atomic force probing (AFP) uses very sharp tungsten tips (100nm in radius) which wear out rather quickly, even with the greater durability of tungsten as compared to silicon. This paper demonstrates how worn tips that no longer image and probe properly can be reconditioned using the focus ion beam (FIB) tool. The method works best for tips that are under approx. 750nm in diameter and are not bent. It works well for freshly manufactured tips that do not work properly due to mishandling or improper storage which allowed particulates/oxide to build up on the tip. The method also works well for fresh tips that have been worn down (or slightly bent) after several hours of scanning and probing. This method is straightforward and requires a minimal amount of time. Typically, four probe tips can be reconditioned in about 30 minutes on the FIB.

Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.