Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

In this paper, the effects of an open defect resulting in floating gate on combinational logic gate structures are studied. From this study, a novel method is derived to predict and narrow down the potential open defect location from a long failure path that is driving multiple branches of input nodes, into a much smaller segment without EBAC analysis. This method is applied with great success to localize open defects on actual low yield cases from advanced technology nodes with significant reduction in FA cycle time.

EeLADA has been introduced previously as a prospective alternative approach to DFT scan diagnosis for scan logic defect localization. It has the capability to reveal induced signals from laser stimulation that are relevant to the failure signature by comparing failing pins and cycles of the bad device. Multiple schemes involving different combinations for comparison are possible. Defect simulations based on cell fault injections on a multi-level logic of a real digital device circuit characterizes the different comparison schemes. The findings are used to devise an optimized methodology to determine suspected fail locations to guide physical failure analysis to reveal the defect. A successful case study substantiates the method.

This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.

The case study in this paper describes how collaboration between customer design and test teams and a thorough FAB investigation triggered by a detailed electrical analysis using the Atomic Force Nanoprober (AFP) resulted in the effective resolution of a challenging implant related issue on LDMOS structure that caused yield loss. The quick success in this case has led to a shorter yield ramp cycle on this new product for mass production.

This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.

This paper describes a sample preparation methodology for Trench Power MOSFET that significantly improved our failure analysis success rate for trench bottom defect. With precise fault localization and subsequent a unique physical failure analysis using parallel polishing method on Trench Power MOSFET, This enabled defect detection from the trench top to the trench bottom.

In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.

This paper describes a low yield case which results in a unique 68 mm single ring wafer sort failure pattern. A systematic problem solving approach with the application various FA techniques and detailed Fab investigation resolved the issue. The root cause for the unique ring failure pattern was due to a burr at the implanter load lock. The burr scratched and toppled the photoresist resulting in subsequent blocked well implantation and memory failure.

This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.