Reliability of low standby current (Isb) CMOS circuits is impacted by extremely small non-fault resistive defects which, without compromising logic functionality or timing specifications, cause Isb currents well in excess of device specifications. A primary cause of high Isb, identified through failure analysis, is due to Crystal Originated Pits (COPs) defects, whereat thin oxide is more prone to electrical breakdown.

Both photo- and thermal emission analysis techniques are used from the backside of the die colocate defect sites. The technique is important in that process and package technologies have made front-side analysis difficult or impossible. Several test cases are documented. Intensity attenuation through the bulk of the silicon does not compromise the usefulness of the technique in most cases.

The dependence of a defective device's voltage-current characteristics on temperature is studied, both from a theoretical perspective and through a series of actual case studies. The shape of the current vs. temperature curve is shown to be a good prognosticator of the defect type, and as such a valuable complement to other non-destructive defect characterization techniques such as photoemission spectrum analysis [1].