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1-11 of 11
Rudolf Schlangen
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Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 153-162, October 30–November 3, 2022,
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Near Infra-Red (NIR) techniques such as Laser Voltage Probing/Imaging (LVP/I), Dynamic Laser Stimulation (DLS), and Photon Emission Microscopy (PEM) are indispensable for Electrical Fault Isolation/Electrical Failure Analysis (EFI/EFA) of silicon Integrated Circuit (IC) devices. However, upcoming IC architectures based on Buried Power Rails (BPR) with Backside Power Delivery (BPD) networks will greatly reduce the usefulness of these techniques due to the presence of NIR-opaque layers that block access to the transistor active layer. Alternative techniques capable of penetrating these opaque layers are therefore of great interest. Recent developments in intense, focused X-ray microbeams for micro X-Ray Fluorescence (μXRF) microscopy open the possibility to using X-rays for targeted and intentional device alteration. In this paper, we will present results from our preliminary investigations into X-ray Device Alteration (XDA) of flip-chip packaged FinFET devices and discuss some implications of our findings for EFI/EFA.
Proceedings Papers
ISTFA2020, ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis, 116-121, November 15–19, 2020,
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Working on wafer-level has been the only way of performing electrical failure analysis (EFA) without the need for die-packaging. The introduction of Si-interposer based 2.5D packaging, with high bandwidth memory (HBM) stacks surrounding our GPU chip, drastically increasing packaging turn around times from approximately 3 days to 3-4 weeks. Having to wait more than 3 weeks for EFA and debug work of 1st Silicon chips is a significant risk for chip bring-up. To address these challenges, this paper presents different ways of reusing the existing wafer-level EFA tool for single die EFA, and introduces a concept for a novel and dedicated single die tool. Additionally, singulated die fixturing and support windows are designed to enable the usage of a 2.45 Numerical Aperture Solid Immersion Lens, and first results from a near reticle limited 16 nm Fin-FET GPU product are also presented.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 86-98, November 10–14, 2019,
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High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 179-181, November 10–14, 2019,
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Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 7-18, November 6–10, 2016,
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Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 51-54, November 6–10, 2016,
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Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.
Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 161-165, November 6–10, 2016,
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Visible Light (or Laser) Probing (VLP) is an exciting new development in Laser Voltage Probing (LVP) technology because it promises a dramatic improvement in resolution over current Near Infrared (NIR) solutions [1-3]. To have adequate visible light transmission for waveform probing and modulation mapping, however, ultrathinning of the silicon backside to <2-5 μm is required. The use of solid immersion lens (SIL) technology places additional requirements on sample preparation. In this paper, we present a simple, SIL compatible technique for VLP sample preparation.
Proceedings Papers
ISTFA2012, ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis, 316-324, November 11–15, 2012,
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This paper describes the application of lock-in thermography (LIT) for flip-chip package-level failure analysis. LIT successfully detected and localized short failures related to both die/C4 bumps and package defects inside the organic substrate. The detail sample preparation to create short defects at different layers, LIT fault isolation methodology, and case studies performed with LIT are also presented in this paper.
Proceedings Papers
ISTFA2011, ISTFA 2011: Conference Proceedings from the 37th International Symposium for Testing and Failure Analysis, 68-73, November 13–17, 2011,
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With the growing variety, complexity and market share of 3D packaged devices, package level FA is also facing new challenges and higher demand. This paper presents Lock-In Thermography (LIT) for fully non-destructive 3D defect localization of electrical active defects. After a short introduction of the basic LIT theory, two slightly different approaches of LIT based 3D localization will be discussed based on two case studies. The first approach relies on package internal reference heat sources (e.g. I/O-diodes) on different die levels. The second approach makes use of calibrated 3D simulation software to yield the differentiation between die levels in 8 die µSD technology.
Proceedings Papers
ISTFA2010, ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis, 191-195, November 14–18, 2010,
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This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.
Proceedings Papers
ISTFA2009, ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis, 21-26, November 15–19, 2009,
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Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.