The need for reverse engineering (for IP verification or for reproducibility) has reached unprecedented levels requiring not only the inspection of the circuitry but also the understanding of the packaging and interconnects. Achieving the best X-ray inspection for a particular application depends on an in-depth understanding of the X-ray system configuration, the sample configuration, and the sample preparation techniques available. This paper presents various case examples on the development of advanced X-ray inspection techniques for IC reverse engineering, along with information on the limitations of X-ray imaging, issues with 3D reconstruction, models for resolution configuration improvement, and advantages and disadvantages of advanced sample preparation techniques. It is observed that the novel X-ray inspection techniques, combined with appropriate sample prep techniques, provide the necessary resolution to achieve results necessary for current reverse engineering needs.

It is known by both the commercial and government suppliers, one of the best ways to guarantee the security and reliability of IC's is to image the IC directly using an x-ray microscope. These images can be inspected for many signs of counterfeit electronics. Unfortunately, previous generations of x-ray imaging systems have not kept up with the increasingly sophisticated counterfeiting techniques. Traditional 2D X-ray inspection techniques are becoming inadequate for imaging and verifying features due to the limited resolution of these systems for thick samples and because 2D images contain too many overlapping features to easily discern, making identification very difficult. This paper discusses the development of advanced sample preparation techniques for counterfeit IC detection. It presents information on the limitations of X-ray imaging and 3D tomographic reconstruction, and on the models for resolution configuration improvement.

The X-ray inspection of fully assembled samples is becoming ever more important as the benefits of using area array packages/chip scale packages/flip chips are applied to more and more products. Sample preparation has traditionally been used to improve access to geometry or a specific location with a known defect that requires verification. The novel paradigm is an integrated approach to sample preparation and X-ray inspection to optimize resolution and throughput time performance with minimally deprocessed sample. This paper, covering the limitations of X-Ray imaging and 3D tomographic reconstruction, discusses the development of models for throughput time and resolution by failure analysis labs. It also discusses the processes involved in advanced sample preparation techniques and global BGA removal to obtain improved resolution at die level.