Skip Nav Destination
Close Modal
Update search
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
NARROW
Format
Topics
Subjects
Book Series
Article Type
Volume Subject Area
Date
Availability
1-12 of 12
Rommel Estores
Close
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
Sort by
Series: ASM Technical Books
Publisher: ASM International
Published: 01 November 2023
DOI: 10.31399/asm.tb.edfatr.t56090069
EISBN: 978-1-62708-462-8
Abstract
A typical mobile processor die may contain, among other things, a variety of high-performance as well as low-power processing cores along with 5G modems, Wi-Fi modules, image processors, GPUs, and security modules, with a total transistor count exceeding 10 billion. Such designs pose many challenges for yield ramp and diagnostics. This chapter examines these challenges and the growing demand for innovative solutions to help failure analysts quickly and accurately isolate faults. It also assesses the capabilities and future potential of ATPG scan diagnostics, streaming scan networks, and advanced fault models for diagnosing embedded memory.
Proceedings Papers
ISTFA2022, ISTFA 2022: Conference Proceedings from the 48th International Symposium for Testing and Failure Analysis, 405-410, October 30–November 3, 2022,
Abstract
View Paper
PDF
The success of failure analysis and related investigations rely on the quality of information made available to the investigating team. When die level traceability (DLT) is implemented on the product, the actual location of a particular unit in the wafer and all the available data can be traced back and pieced together to reveal insights on the possible root cause( s). The data for the specific unit can be determined, then analyzed and compared with the lot distribution to check for any information that could help the analyses and investigations. With access to the original data, a failing unit can be investigated to determine which data have changed which can prove essential to the direction of failure analysis approach. Four case studies will be discussed to demonstrate how DLT enabled fast, accurate and detailed root-cause identification leading to effective corrective and preventive actions.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 84-95, October 31–November 4, 2021,
Abstract
View Paper
PDF
Dynamic analysis by laser stimulation (DALS) is a method used to analyze temperature-dependent failures. There are cases, however, where the laser alone cannot get devices hot enough to induce an observable change in behavior. This paper examines three such cases and describes how analysts were able to induce and diagnose the underlying failure by using external signals, complex triggering, and resistive heating to compensate for limitations in laser power.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 366-368, October 31–November 4, 2021,
Abstract
View Paper
PDF
This paper explains how the authors determined the cause of a fast-to-rise failure discovered during scan chain testing of an image sensor. The failed device was mounted on a portable card that facilitates transfer between test platforms in an electro-optical probing (EOP) system. Initial fault localization was conducted through backside PEM, but the results were inconclusive. The part was then analyzed on a digital scan chain tester to check for flaws in the daisy chain of shift registers. Through broken scan chain analysis, the potential cause of the problem (a failing flip-flop) was narrowed down to a few chain links and ultimately pinpointed using EOP fault isolation techniques. The failed device was then deprocessed by parallel lapping and analyzed in a SEM, revealing a broken poly gate as the physical cause of failure.
Proceedings Papers
ISTFA2021, ISTFA 2021: Conference Proceedings from the 47th International Symposium for Testing and Failure Analysis, 377-387, October 31–November 4, 2021,
Abstract
View Paper
PDF
For unique single failures, which tend to be the case in customer return and reliability failures, selecting another sample or performing root cause deconvolution is not an option, and if diagnostic tests are not conclusive, it becomes necessary to extend the effectiveness of automatic test pattern generator (ATPG) diagnosis in order to determine the failure mechanism. This paper proposes a way to improve resolution using single-shot logic and high-resolution targeted patterns. Two cases are presented to demonstrate the approach and show how it performed on actual failing units.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 140-147, November 10–14, 2019,
Abstract
View Paper
PDF
Some of the most challenging task in analyzing fractures is a die that has not been fully cracked apart and a cracked die with electrical overstress damage. Traditional tools such as simple magnifying lens, optical microscope and up to the advance Scanning Electron Microscope are not enough to study the internal fractures or markings that could lead back to the origin of the crack. In order to study these internal fractures, the analyst tends to break the sample into pieces. However, this method creates additional mechanical stress and leads to a secondary crack where the point of origin will be difficult to analyze. This paper aims to introduce infrared microscopy in fractography (mainly on silicon) using cases and techniques to minimize the occurrence of secondary crack in analyzing internal fractures.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 182-191, November 10–14, 2019,
Abstract
View Paper
PDF
In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.
Proceedings Papers
ISTFA2019, ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis, 419-425, November 10–14, 2019,
Abstract
View Paper
PDF
This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 141-147, October 28–November 1, 2018,
Abstract
View Paper
PDF
The advent of lock-in thermal imaging application on semiconductor failure analysis added capability to localize failures through thermal activity (emission) of the die. When coupled with creative electrical set-up and material preparations, lock-in thermography (LIT) [1, 2] application gives more possibility in exploring the failure of the device using low power settings. This gives higher probability of preserving the defect which leads to a more conclusive root cause determination.
Proceedings Papers
ISTFA2018, ISTFA 2018: Conference Proceedings from the 44th International Symposium for Testing and Failure Analysis, 449-459, October 28–November 1, 2018,
Abstract
View Paper
PDF
ATPG diagnosis is an essential part in failure analysis and is proven to be an effective technique in isolating faults in the digital core. In many single failure cases however, ATPG diagnosis could yield either incorrect candidates or includes a large amount of equivalency which limits diagnostic resolution. While iterative ATPG diagnosis improves diagnostic resolution, there are many cases where the resolution is still insufficient. This paper will discuss a methodology that helps the analyst understand and complement ATPG diagnosis by using an approach called “single shot logic patterns”. New patterns that each target one singular fault in the area of interest provide the failure analyst with simplified analytical data. This process is repeated for each suspect candidate. The number of times a target fault is detected is increased for better resolution. Aggregating this analytical data with the layout and fan out of the net instances could provide greater resolution into the likely defective area. Furthermore, adding constraints can also be used to further simplify the test and/or control the fan out of failures. Only equivalencies where there is observable fan out can achieve greater diagnostic resolution. ATPG tools have been observed to not always maximize this fan out.
Proceedings Papers
ISTFA2017, ISTFA 2017: Conference Proceedings from the 43rd International Symposium for Testing and Failure Analysis, 526-537, November 5–9, 2017,
Abstract
View Paper
PDF
This paper will present a practical implementation of ATPG testing and diagnosis in Failure Analysis resulting in a fast and efficient iterative ATPG diagnosis and fault isolation. On this implementation, a compact test HW instead of an ATE is used for cost-effective ATPG testing and characterization capability. The advantages of this implementation are combined with ATPG tools to make it possible to achieve a faster and more efficient implementation of iterative ATPG diagnosis, Dynamic Analysis by Laser Stimulation (DALS) analysis or similar techniques. The requirements needed in order to implement ATPG testing and diagnosis in FA lab will be discussed. Success in determining root cause, especially on the complex analysis cases is determined by the complimentary combination of various fault isolation techniques. Knowledge of the fundamentals of these techniques combined with creative thinking process of the analyst leads to the approaches and solutions that maximize the combined advantages of these techniques.
Proceedings Papers
ISTFA2014, ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis, 436-445, November 9–13, 2014,
Abstract
View Paper
PDF
The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.