Failure Analysis has to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits mapping channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: a two-transistor cell (2T-cell) from Atmel and a one-transistor cell (1T-cell) from STMicroelectronics.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical Scanning Probe Microscopy (SPM) based techniques such as Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM) are used to directly probe floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the gate proves to be the key problem, more than the probing technique itself. Applications are demonstrated on 128 kbit EEPROMs from ST Microelectronics and 64 kbit EEPROMs from Atmel.

Magnetic field based techniques have shown great capabilities for investigation of current flows in integrated circuits (ICs). After reviewing the performances of SQUID, GMR (hard disk head technologies) and MTJ existing sensors, we will present results obtained on various case studies. This comparison will show the benefit of each approach according to each case study (packaged devices, flip-chip circuits, …). Finally we will discuss on the obtained results to classify current techniques, optimal domain of applications and advantages.

The use of time resolved photon emission (TRPE) to compare internal measurements with simulations can dramatically reduce the time required for IC analysis. During debug, this technique makes it possible to probe only transistors of interest. Two limitations must be overcome: precise location of transistor photon emission areas and distinction between photons emitted by closely spaced transistors. Otherwise results may be seriously biased. Introducing CAD auto-channeling for TRPE makes it possible to generate virtual layers where emissions are expected. As a result, transistor TRPE areas can be automatically located and emission from nearby transistors is taken into account, thus significantly reducing the duration of IC analysis.

Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

Defects localization from the IC’s backside using hot spot detection techniques is discussed. Simulations are used to validate the applicability of hot spot detection from the silicon backside and to determine the optimal experimental conditions. The effects of the dissipated power, the substrate thickness and the defect position relative to the chip area are studied. These simulations take into account the thermal dependence of the silicon thermal conductivity. Transient simulations are also performed to evaluate the effect of modulating the power on the backside temperature difference. Backside Liquid Crystal Microscopy as well as Infrared Thermography and Thermal Laser Stimulation results on defective ICs are presented.

The application of laser beam based techniques for ESD defect localization in silicon and gallium arsenide integrated circuits is studied. The Thermal Laser Stimulation technique (OBIRCH, TIVA) is shown to precisely localize electrostatic discharge (ESD) defects under low voltage and current consumption, thus avoiding device or defect degradation upon testing. It is also shown that nonbiased Thermal Laser Stimulation (SEI) tests can localize ESD defects in the silicon substrate. Physical analysis revealed that a thermocouple composed of molten silicon with crystalline silicon generated a Seebeck voltage sufficiently large to be detected. Finally, the pulsed Optical Beam Induced Current technique (OBIC) under no bias condition was evaluated and compared to both biased and nonbiased Thermal Laser Stimulation techniques. It proved to be complementary as it offers a different insight into the ESD induced degradation.

An increasing number of analysis techniques requires access to the backside silicon of a functional device. For backside sample preparation of packaged devices, CNC milling tools can perform both package opening and circuit preparation. They offer good versatility in terms of type and size of packages – from ceramic to exotic plastic molding. They are suited for precise silicon thinning as well as polishing. Finally, the automation and software control of the process offer good reproducibility of chip opening and preparation. For some applications, the silicon substrate needs to be thinned as closely as possible to the circuitry with a uniform thickness (less than 100 microns). Bent silicon surfaces are challenging for backside sample preparation. This is the case of C4 packages or large plastic TSOP packages. Conventional approaches would cut off the top of the bent surface. From small flat surface to large bent silicon dies, we will detail our technique for thinning silicon to a uniform thickness with extreme precision. Finally, we will characterize the final surface roughness which plays an important role in backside techniques.

While integrated circuits are routinely modified using Focused Ion Beam systems (FIB), the reliability of these modifications has not yet been thoroughly studied. For several years, researchers at Sandia National Labs and CNES have been involved in the evaluation of the impact of FIB exposure on semiconductor structures. We have all come to the same conclusion: the intrinsic behavior of a circuit is altered after FIB intervention and the damage cannot be completely recovered but can be controlled. Despite these results, modified circuits are used in many applications such as satellites or even more critical environments. Although FIB modifications are invasive to the circuit they provide a working sample that can prove out, in silicon, a design change. However, is the functionality of FIB modified ICs reliable? In more practical terms: Can we use modified devices for our applications and what guarantee do we have that they will work after a few months? To answer these questions, we have conducted extended studies addressing both MOS and bipolar circuits. We used basic structures (such as transistors and diodes) and complex structures (operational amplifiers, oscillators, etc) and studied the effects of two different FIB systems, a Schlumberger P2X and an FEI Vectra 986. We have investigated the reliability of the devices by monitoring intrinsic parameters, before FIB, after FIB, during life testing and after life testing.

This paper presents a comparative study of backside sample preparation techniques with applicability to conventional as well as flip chip package types. We will cover mechanical (grinding and milling tools), chemical (wet and dry chemistries) and other approaches such as laser ablation. Backside sample preparation is very challenging. The preparation process flow starts with decapsulation of the ceramic or plastic package, continues with the die paddle removal, silicon thinning and finishes with silicon polishing. The techniques involved include mechanical, chemical and other novel approaches for ceramic and plastic package. Today, only CNC milling can cover the whole process for almost any kind of packages. Nevertheless, photo ablation is a rising technology for package decapsulation. In addition, chemical wet etch can be used to perform silicon thinning and polishing. We will illustrate the complexity of the process through examples. The first one is a ceramic package where the main issue is the hardness of ceramic. The second one is a TSOP package where the main challenge is the chip scaled package. Both will be observed through the IR emission microscope to demonstrate the efficiency of the preparation.

Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

IDDQ testing detects a majority of faults in logic ICs. To improve defect coverage with very short test patterns, IDDQ testing has been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms. Nevertheless, for failure analysis purposes, this progress has not eliminated the complex task of fault isolation at the silicon level of ICs. Defect localization is facilitated with IDDQ testing because the defect is detected as soon as it is activated inside the device. At the failed vector, abnormal IDDQ current is measured and accurate localization of the corresponding defect inside the chip can be performed. Thermally related techniques or emission microscopy can be used for this localization process. Very powerful tools like electron beam testers can also be used to deeply analyze faulty devices by internal contactless testing. In this paper, we will present an application of IDDQ testing for fault detection and some key issues regarding localization of the corresponding defect: • Appropriate techniques, • Switching from electrical testing to fault localization, • Modifying the test pattern to shorten the localization process, • Constructing a localization method based on an IDDQ diagnostic.

Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.

Recent progress with IDDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. IDDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation (ATPG) algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. To deal with the challenge of faster and more accurate defect localization with greater sensitivity, we have developed a new method based on voltage contrast capabilities for internal localization of IDDQ defects. This method covers an extended range of cases: functional or non functional devices, with or without CAD information, etc... Using only the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located. This approach can also be extended to coupling with netlist information. For example, the equipotential line previously found on the faulty circuit can be compared with the fault simulator output. Then, the site of the simulated defect corresponding to the physical failure can be extracted and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.