This paper covers methods used to isolate single leaky junctions in a test structure designed for Flash memory technology development. It may be possible to isolate this failure through micro probing or a combination of electrical testing and physical structure modification by FIB, but at the expense of spending numerous days. The paper shows that a combination of emission microscopy (EMMI), electron beam induced current (EBIC) characterization and a SEM nano-probing can drastically simplify the fault isolation process. Results of nano-probing are also shown to prove the level of leakage detected in the faulty junction. A combination of EMMI and EBIC characterization was able to pinpoint the problematic junction from approximately 2500 junctions in the structure. Furthermore, the nano-probing IV characterization proved the identified junction to be indeed high in leakage current, providing further confidence for physical failure analysis.

Non-visual fails have become an ever present complication in the IC industry. Nano probing SRAM bit cells at the inverter level allows the cell to be tested and static noise margin (SNM) to be measured. This paper explains how nano probing of a 65nm technology 6 transistor bit cell was performed and SNM dependence on supply voltage was measured for both hold and read modes. Connection to the bit cell was made at the Metal 1 layer with 7 nano probes to collect the voltage transfer curves (VTCs) of the two inverters of the cell. In this experiment, each inverter was tested by varying Vdd voltage from 1.5, 1.2, 1.0, 0.8, 0.6, 0.4 and 0.2V while collecting the VTC. The two VTCs of the cell are plotted to produce the cell’s butterfly curve from which the SNM is found graphically for each setting of Vdd.