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Raymond Mendaros
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Proceedings Papers
Alex Marionne del Castillo, Alfred Jay Rafael, Jolina May Matibag, Jae Saladar, Robin Evangelista ...
ISTFA2024, ISTFA 2024: Conference Proceedings from the 50th International Symposium for Testing and Failure Analysis, 427-433, October 28–November 1, 2024,
Abstract
View Papertitled, Effective FA Approach in Uncovering Gate-to-D/S Tungsten Spur Fabrication Defect
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for content titled, Effective FA Approach in Uncovering Gate-to-D/S Tungsten Spur Fabrication Defect
A series of power supply line controller failures at Analog Devices Incorporated (ADI) exhibited abnormal output voltage and quiescent current symptoms. Our failure analysis revealed a gate-to-drain/source tungsten spur defect, which required a sophisticated multi-step detection process. The investigation combined several advanced techniques: light emission microscopy (LEM) and optical beam induced resistance change (OBIRCH) identified the failing circuit, passive voltage contrast (PVC) located the affected transistor, and nanoprobing with electron beam induced resistance change (EBIRCh) pinpointed the gate-to-source/drain leakage location. Focused ion beam (FIB) cross-sectioning proved crucial for physical analysis, as conventional chemical deprocessing would have destroyed the tungsten spur and potentially misidentified the defect as electro-static discharge damage. Transmission electron microscopy confirmed the spur's composition as tungsten, and subsequent fabrication investigation traced the root cause to a titanium nitride barrier breach at the contact bottom, occurring where contacts intersect with spacer nitride. The issue was resolved through critical dimension tightening at the fabrication site.
Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 45-53, November 12–16, 2023,
Abstract
View Papertitled, Intricacies in the Failure Analysis of Integrated Capacitors
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for content titled, Intricacies in the Failure Analysis of Integrated Capacitors
Integrated capacitors use metal plates such as in Metal-Insulator-Metal (MIM) and Metal-Oxide-Metal (MOM) capacitors while Polysilicon and Silicon (Si) substrate for metal-oxide-semiconductor (MOS) capacitors. Three major challenges and solutions were discussed in this technical paper. First, the failure site localization of a subtle defect in the capacitor plates. To determine the specific location of the defect site, Electron Beam Induced Current (EBIC) analysis was performed while the part was biased using a nano-probe set-up under Scanning Electron Microscopy (SEM) environment. Second, Failure Mechanism contentions between Electrically Induced Physical Damage (EIPD) or Fabrication process defect particularly, for damage site that is not at the edge of the capacitor and without obvious manifestations of Fabrication process anomalies such as bulging, void, unetched material or shifts in the planarity of the die layers. To further understand the defect site, Scanning Transmission Electron Microscopy (STEM) coupled with Energy-Dispersive X-ray Spectroscopy (EDS) were utilized to obtain high magnification imaging and elemental area mapping. Third, misled conclusion to be an EIPD site manifested by burnt and reflowed metallization. The EIPD site was only a secondary effect of a capacitor dielectric breakdown. This has been uncovered after understanding the circuit connectivity, inspections of the capacitors connected to the EIPD site, fault isolation and further physical failure analysis were performed. As results of the Failure Analysis (FA), Customer and Analog Devices Incorporated (ADI) manufacturing hold lots were accurately dispositioned and related corrective actions were precisely identified and implemented.