This presentation provides an overview of nanoprobe systems and what they reveal about defects and abnormalities in semiconductor device structures and materials. The presentation covers the basic operating principles, implementation, and capabilities of atomic force probe and beam-based imaging techniques, including AFP pico-current contrast and scanning capacitance imaging, SEM/FIB active voltage contrast imaging, and SEM/FIB electron-beam absorbed current (EBAC), induced current (EBIC), and induced resistance change (EBIRCH) imaging. It also includes guidelines for probing transistors and copper metallization and case studies in which nanoprobing was used to analyze gate oxide and substrate defects, intermittent bit cell failures, threshold voltage shifts, and time-domain popcorn noise.

This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

This presentation provides an overview of nanoprobe systems and what they reveal about defects and abnormalities in semiconductor device structures and materials. The presentation covers the basic operating principles, implementation, and capabilities of atomic force probe and beam-based imaging techniques, including AFP pico-current contrast and scanning capacitance imaging, SEM/FIB active voltage contrast imaging, and SEM/FIB electron-beam absorbed current (EBAC), induced current (EBIC), and induced resistance change (EBIRCH) imaging. It also includes guidelines for probing transistors and copper metallization and case studies in which nanoprobing was used to analyze gate oxide and substrate defects, intermittent bit cell failures, threshold voltage shifts, and time-domain popcorn noise.

Random Telegraph Signal (RTS), also described as popcorn noise in semiconductor analog circuits occurs when there is a sudden step in threshold voltage for a MOSFET or sudden step in base current for a bipolar transistor. The causes of popcorn noise can be process-related in semiconductor manufacturing. This paper presents a nanoprobe analysis methodology that was able to detect popcorn noise issues in discrete transistors causing analog circuit failure. The results presented for two different devices obtained similar results proving that the analysis methodology is viable for detecting popcorn noise issues in semiconductor MOSFET transistors. From a failure analysis perspective, the purpose of this paper is to provide the ability and a methodology to detect a signal that differentiates a failing transistor (popcorn noise) from a non-failing transistor (no popcorn noise). In this regard, the ability to obtain these results was not only unexpected but also very successful.

This paper presents a case study of a customer return that failed functional testing on the production tester. Investigation by applications and design engineering identified several analog circuit blocks where a possible failure mechanism could be located causing the functional failure mode seen at test. The identified circuit blocks all resided in deep n-well structures preventing traditional passive voltage contrast imaging (PVC) from being used to isolate the fault location. Neither functional probing nor active voltage contrast imaging were viable options to isolate the failure mechanism to a specific node. The analyst, having a good understanding of the principles of PVC and the difficulties associated with PVC imaging of deep n-well circuits, took advantage of a design feature in the device to restore the ability to perform passive voltage contrast imaging on these circuits. Using this enhanced PVC capability, two polysilicon capacitors with degraded oxide integrity were easily identified. This degraded oxide was verified to cause abnormal leakage to the substrate by means of nanoprobe analysis. Without identifying and taking advantage of a design feature not intended for failure analysis, locating these damage poly capacitors would have been extremely difficult because existing analysis techniques could only localize the failure to a number of circuit blocks. This paper presents a brief detailed over-view of PVC imaging, the issues with PVC imaging of deep n-well circuits, and an example of a previous attempt to overcome the deep n-well PVC problem. This review is then followed by the case study demonstrating the steps taken to restore PVC capability and concludes with recommendations for design for failure analysis (DFA).

The physical analysis of sub-100nm device technologies in many cases requires the total or partial removal of the multiple layers of metallization that route electrical signals and power through the device. This paper presents a simple and quick polishing technique that will remove the entire metallization stack above metal 1 for a 55nm technology device, which results in significantly reducing the time needed to reach the transistor level of the device and also greatly improving uniform planarity across the device. This method is intended for those cases in which gaining access to the transistor layer is required for electrical characterization and physical analysis. The improved speed of this polishing technique to reach the transistor layer has greatly reduced cycle time. The results for the polishing method have been relatively reliable with over a 95% success rate.

The relationship between blocked or depleted lightly doped drain (LDD) implants and threshold voltage (Vt) shifts resulting in suppressed drive current has been thoroughly investigated and characterized through nano-probe analysis. In this paper, a review for a technique for characterizing Vt shift failures is presented as well as a brief review of the LDD Vt shift failure. A case study is also presented showing the characterization, identification, and the physical analysis results for the symmetrical Vt shift failure mechanism. The method presented allows the analyst to differentiate between a Vt shift failure caused by a depleted LDD implant mechanism and a failure caused by dopant depletion in the gate poly-silicon. The results demonstrate that there are now at least two failure mechanisms that can be responsible for threshold voltage failures and it is likely that there are more that have yet to be discovered.

This paper presents case studies that examine low voltage, low current electrical characterization and analysis of data that could help identify root cause failure mechanisms for soft transistor failures, providing a review of Vt shifts and blocked LDD implants review. The case studies demonstrate the importance of getting the most information possible out of all aspects of the nanoprobe electrical characterization results for failing transistors. Technology computer aided design (TCAD) modeling of transistor defects will be a useful tool for the nanoprobe analyst to identify the subtle defects that can only be identified through careful electrical characterization in conjunction with process analysis and experiments by the manufacturing facility. However, modeling at the transistor level has its difficulties. The key will be to build a library of electrical signatures with corresponding defects as they are discovered.

The use of atomic force probe (AFP) analysis in the analysis of semiconductor devices is expanding from its initial purpose of solely characterizing CMOS transistors at the contact level with a parametric analyzer. Other uses found for the AFP include the full electrical characterization of failing SRAM bit cells, current contrast imaging of SOI transistors, measuring surface roughness, the probing of metallization layers to measure leakages, and use with other tools, such as light emission, to quickly localize and identify defects in logic circuits. This paper presents several case studies in regards to these activities and their results. These case studies demonstrate the versatility of the AFP. The needs and demands of the failure analysis environment have quickly expanded its use. These expanded capabilities make the AFP more valuable for the failure analysis community.

Traditional micro-probing and electrical characterization at the transistor level for sub-100nm technologies has become very difficult if not virtually impossible. Scanning probe microscopy technology specifically atomic force probing was developed in response to these issues with traditional micro-probing. The case studies presented in this paper demonstrate how atomic force probing was used to characterize failing sub-100nm transistors, identify possible failure mechanisms, and allow device/process engineers to make adjustments to the wafer fabrication process to correct the problem even though physical analysis with scanning election microscope/transmission electron microscope was not able to image and identify a failure mechanism. The probable causes for the transistor level failures are being identified through test methods, computer simulations, and electrical analysis by means of the atomic force probe after the failure has been sufficiently localized to a minimum number of transistors.

Passivation damage, a common failure mode in microelectronics circuitry, can be easily identified by optical inspection in the form of a local 'discoloration' after exposing the die to a chemical that would penetrate through the crack and attacks metal lines. Unfortunately, this process destroys evidence of what damaged the passivation, since it attacks the damaged region. As a result, in many cases, the mechanism by which the passivation damage occurred is unclear. This problem is addressed in this paper by a procedure to examine passivation damage by transmission electron microscopy (TEM) of a cross-section sample prepared from the backside and without exposing the die from the top side. The backside approach was successfully used to assign the root cause of the passivation damage to packaging process. A topside approach to characterize the passivation damaged region can result in destruction of evidence at the defect location.

The identification of foreign material at metal-oxide interface or at the poly-substrate interface by means energy dispersive spectroscopy (EDS) is very difficult. Auger depth profiling can be used as an alternative method to cross-section EDS analysis for the identification of very thin layers of foreign material in semiconductor devices. This article presents a sample preparation method adapted from a planar transmission electron microscopy sample preparation method so that Auger depth profiling can be used as a practical tool for identifying very thin layers of foreign materials at interfaces buried deep within semiconductor devices. The discussion covers the advantages, applications, and the procedure for performing the analysis. The high degree of control provided by the method gives an analyst the ability to easily thin down material layers to less than 100nm of a target layer, thereby significantly reducing sample preparation time as well as analysis time on the Auger tool.

This paper provides failure analysis engineers a simple method for constructing probe pads on failing 0.12um SRAM bit cells using the FEI 820 Focused Ion Beam (FIB) tool. This method allows for the easy location of the failing bit cell, results in good electrical isolation, and only takes a minimal amount of FIB time (2 hours for 6 pads). The method is effective for all technologies 0.12um or greater with a high success rate once the analyst is proficient in its use. Once probe pads have been constructed, it is then relatively easy for an analyst to perform electrical analysis to identify the defect type and location causing the bit cell failure before the physical analysis is performed.

DuPont EKC265 Post Etch Residue Remover has been available for many years as post reactive ion etch photo-resist etchant for semiconductor wafer processing. It has also proven useful for the physical analysis of failing semiconductor devices. This paper shows how EKC265 can be used as copper metallization wet etchant to aid in the physical deprocessing. It provides the EKC265 copper metallization etch results and physical deprocessing results using EKC265. An ancillary effect of wet etching copper metallization rather than removing by means of mechanical polishing is that only the thin layer of underlying barrier metal layer has to be removed by means of mechanical polishing. As the barrier metal is a metal-silicon nitride compound, the polishing rate to remove it is close to that of the surrounding oxide. Therefore, less total polishing time is required to remove the copper metallization layer when EKC is used.

Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.