Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.

Focused Ion Beam (FIB) circuit edit (CE) has been playing a pivotal role in providing insight to ramp-up yield. Numerous IC fabrication processes inherently pose unique challenges to FIB circuit edit approaches. Copper (Cu) has been the material of choice for interconnects as technology features shrink to the 180 nm node and below. Thick copper planes are used for multiple reasons that are mentioned later. Milling through thick copper planes has been tremendously challenging and time consuming during FIB circuit edits. Proposed is a methodology to enhance the bulk Cu removal process at astounding etching rates while maintaining planarity.

For more than 10 years, silicon thinning techniques have been relegated to an art form of mere necessity to enable complex optical probing and circuit edit analysis. Silicon thinning is a fundamental aspect of diagnostic analysis and while it is well-understood that limitations in the area of silicon thinning can severely limit high-quality diagnostic results, poor thinning results have generally been accepted as standard environmental operating conditions with which optical probe and circuit edit engineers must cope. Presented here is a scientific approach to thinning silicon to enable predictable high-precision, high-quality results. Remaining silicon thickness (RST) has been debated throughout the years because it was uncertain how much thinning was excessive. Primary perceived limitations included mechanical constraints (package / die warping) and post-thinning thermal control. Adding to the complexity of the discussion has been the fact that RST has been largely uncertain because analysis usually involved determining how much silicon was removed rather than how much silicon remains. All of these challenges have been overcome. A novel process has been developed to ultra-thin bulk Si to as low as 10um remaining Si thickness, eliminating the need for the Laser Chemical Etcher for circuit edit and improving optical emission probing considerably. This sample preparation process has been used on Intel Core2 Duo products with a success rate of 98%. Post FIB unit testing is a critical step in this debug process. A technique was developed to calibrate the change in thermal resistivity of the ultra-thin unit such that it will remain within 100ps of its original FMax performance in 90% of tests.