Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Developed procedures to deposit narrow (<100nm), closely spaced, low resistance conductors which exhibit good electrical isolation are demonstrated. The process parameters which limit how narrow a line can be deposited and the methods used to work-around these are discussed. For these depositions, 3pA ion beam current was used with a Mo(CO)6 precursor chemistry. The deposition method minimized the incorporation of non-conductive precursor by-products. To isolate adjacent conductors, a copper etch Credence FIB chemistry was used. The advantages of this procedure over the common practice when XeF2 chemistry is used is also discussed and demonstrated.

Novel Fabry Perot [1] fringe analysis techniques for monitoring the etching process with a coaxial photon-ion column [2] in the Credence OptiFIB are reported. Presently the primary application of these techniques in circuit edit is in trenching either from the front side or from the backside of a device. Optical fringes are observed in reflection geometry through the imaging system when the trench floor is thin and semi-transparent. The observed fringes result from optical interference in the etalon formed between the trench floor (Si in the case of backside trenching) and the circuitry layer beyond the trench floor. In-situ real-time thickness measurements and slope correction techniques are proposed that improve endpoint detection and control planarity of the trench floor. For successful through silicon edits, reliable endpoint detection and co-planarity of a local trench is important. Reliable endpoint detection prevents milling through bulk silicon and damaging active circuitry. Uneven trench floor thickness results in premature endpoint detection with sufficient thickness remaining in only part of the trench area. Good co-planarity of the trench floor also minimizes variability in the aspect ratios of the edit holes, hence increasing success rates in circuit edit.

Circuit edit techniques have been developed for silicon-on-insulator (SOI) devices using a coaxial photon-ion column. Novel trenching, navigation and milling methods, utilizing sub pico-Amp beam currents provide enhanced capability for editing devices with decreased geometries including buried (Box) thickness. Flat trenches 200x200µm were obtained using real time optical fringe monitoring with 125nm accuracy with 950nm λ and FIB bit map milling to adjust for parallelism to the ILD0. This bit map milling technique controlled the etch rate to maintain trench flatness by correlating the optical fringes to the bit map grayscales to vary the dwell time of the ion beam across the trench floor. Through highly accurate, CAD directed beam deflection control, beam placement accuracy in the sub 20nm regime can readily be accomplished, sub pA beam currents provide ultracontrolled etch rates and high aspect ratio (HAR) capability. Complete process definitions, techniques and results are reported. These techniques have proven successful in circuit edit below 90nm, and are expected to meet future technology circuit edit requirements down to 45nm.