In this paper, we demonstrate that lock-in thermography (LIT) appears as a key and complementary technique for Failure Analysis across different use cases. Even if the failure requires a complex emulation setup, thanks to a specific capability of our thermal system, this kind of failure can be addressed. In our FA case study, we will show that LIT is a most efficient solution to address a bridge defect located inside a complex logic area, and furthermore that LIT highlights the defect itself and not only the consequences of the defect.

Editing inside an integrated circuit (IC) is critical to debug new devices. Current flipchip circuit edit techniques are limited by spot resolution and chemistry constraints of Focused Ion Beam (FIB) systems. The newly proposed technique for circuit edit (CE) employs FIB to contact circuit nodes directly on transistor level, offering a wide range of applications since it allows accessing every signal on a chip. The general functionality and the influence on chip performance are evaluated for an Intel 65nm process technology.

Backside circuit edit techniques on integrated circuits (ICs) are becoming common due to increase number of metal layers and flip chip type packaging. However, a thorough study of the effects of these modifications has not been published. This in spite of the fact that the IC engineers have sometimes wondered about the effects of backside circuit edit on IC behavior. The IC industry was well aware that modifications can lead to an alteration of the intrinsic behavior of a circuit after a FIB edit [1]. However, because alterations can be controlled [2], they have not stopped the IC industry from using the FIB to successfully reconfigure ICs to produce working “silicon” to prove design and mask changes. Reliability of silicon device structures, transistors and diodes, are investigated by monitoring intrinsic parameters before and after various steps of modification.

Direct measurements of circuit node signals without changing the performance of the circuitry are essential in modern FA but often impossible for recent IC technologies. This paper shows new methods, based on FIB backside circuit edit, allowing access to every existing circuit node at the device level, and discusses options for probing and discrete characterization.

One method of dynamic probing in modern integrated circuits (ICs) is performed through the backside of the device. The established techniques are limited in lateral resolution because they use infrared (IR) light. This paper demonstrates how state of the art FIB circuit edit (CE) processes enable the application of E-Beam probing through chip backside on current and future IC technologies with low risk of device performance degradation.

The feasibility of low-ohmic FIB contacts to silicon with a localized silicidation was presented at ISTFA 2004 [1]. We have systematically explored options in contacting diffusions with FIB metal depositions directly. A demonstration of a 200nm x 200nm contact on source/drain diffusion level is given. The remaining article focuses on the properties of FIB deposited contacts on differently doped n-type Silicon. After the ion beam assisted platinum deposition a silicide was formed using a forming current in two configurations. The electrical properties of the contacts are compared to furnace anneal standards. Parameters of Schottky-barriers and thermal effects of the formation current are studied with numerical simulation. TEM images and material analysis of the low ohmic contacts show a Pt-silicide formed on a silicon surface with no visible defects. The findings indicate which process parameters need a more detailed investigation in order to establish values for a practical process.