Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

Multiple techniques including electrical resistance measurement plus calculation, cross-sectional view of passive voltage contrast (XPVC) sequential searching, planar and cross-section STEM are successfully used to isolate a nanoscale defect, single metallic stringer in a snakecomb test structure. The defect could not be found by traditional failure analysis methods or procedures. The unique approach presented here, expands failure analysis capabilities to the detection of nanometer-scale defects and the identification of their root causes. With continuous shrinking feature sizes, the need of such techniques becomes more vital to failure analysis and root cause identification, and therefore yield enhancement in fabrication.

This paper presents two cases utilizing high KeV Passive Voltage Contrast (PVC) for defect localization that is impossible with other techniques. The first case is thin layer resistor of CrSi. De-processing or polishing to expose the defective layer may damage it. High KeV PVC combined with FIB etch allows for a clear top view and x-section image. The second case involves a beam sensitive via chain. In order to avoid ion-beam-caused-damage, carbon paste was used to ground the sample. A high KeV electron beam was used to localize the defective via. This paper also discusses the way to avoid beam caused sample damage and how to apply it for further grounding and FIB cross sectioning to reveal the defect.