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Qi Zhang
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Proceedings Papers
ISTFA2023, ISTFA 2023: Conference Proceedings from the 49th International Symposium for Testing and Failure Analysis, 380-383, November 12–16, 2023,
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TEM automation is dedicated to providing high-volume, fast and precise TEM data to enable semiconductor manufacturers to develop and control fabrication processes. It automates TEM operation and measurement procedures, and minimizes the requirements of user training. Traditionally, recipes are required for each specific structure, and Automatic TEM Imaging and Metrology had individual recipes for each structure, respectively and separately. TEM professionals review structures and TEM images and manually assign imaging and metrology recipes one by one. After metrology, it is tedious to manually check mis-measurement of hundreds of TEM images and Critical Dimensions (CDs). In this study, An Intelligent TEM automation process was developed by machine learning process that could “fully” automatically conduct TEM Analysis from Imaging to Metrology starting right after TEM holder insertion without human intervention. It is not limited to automatically prepared TEM samples and also works for manually prepared samples. TEM Auto Metrology is carried out automatically right after Auto Imaging in the background. After that, Auto capturing of mis-measurements can be carried out automatically to catch problematic metrology images and CDs as an invaluable complement. As a result, the whole workflow was streamlined, with better efficiency and accuracy achieved.
Proceedings Papers
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 401-408, November 1–5, 2015,
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Owing to the advancing progress of electrical measurements using SEM (Scanning Electron Microscope) or AFM (Atomic Force Microscope) based nanoprober systems on nanoscale devices in the modern semiconductor laboratory, we already have the capability to apply DC sweep for quasi-static I-V (Current-Voltage), high speed pulsing waveform for the dynamic I-V, and AC imposed for C-V (Capacitance-Voltage) analysis to the MOS devices. The available frequency is up to 100MHz at the current techniques. The specification of pulsed falling/rising time is around 10 -1 ns and the measurable capacitance can be available down to 50aF, for the nano-dimension down to 14nm. The mechanisms of dynamic applications are somewhat deeper than quasi-static current-voltage analysis. Regarding the operation, it is complicated for pulsing function but much easy for C-V. The effective FA (Failure Analysis) applications include the detection of resistive gate and analysis for abnormal channel doping issue.