In this paper we discuss the use of Emission Microscopy (EMMI) to examine the events leading to latchup for various Input/Output (I/O) pins of a test chip in order to study the factors that impact latchup sensitivity of VLSI chips. The goal of our study is to identify and characterize the structures that are most prone to latchup in test chips, thus providing countermeasures to be used to improve the overall latchup resistance of commercial chips. As it has been shown in literature [1-3], EMMI can be used to localize areas that are latching up. Here we focus our attention on electrostatic discharge (ESD) into I/O pins, which may lead to latchup inside I/O circuits or in their proximity.

Picosecond Imaging Circuit Analysis (PICA) is a new technique shown here to be applicable to the analysis of complex VLSI circuits. PICA was used to diagnose a timing failure in the early design of the G6 microprocessor chip. The fault occurred at high frequencies upon consecutive writes. Using PICA, combined with programmable array built-in self test (RAMBIST) techniques, the problem was traced to a race condition in the write control circuits. This allowed timely correction of the design for product implementation.