This paper presents a novel method for determining the Z-depth location of short circuit defects in flip chip packages using lock-in thermography (LIT). The approach analyzes phase shift values from localized hot spots using the LIT system's "Image Statistics" feature, specifically focusing on phase "mean" values at specific lock-in frequencies. Through extensive testing on 2.5D stacked silicon interconnect technology (SSIT) packages exhibiting short failures, we established a strong correlation between phase mean values and the vertical location of defects. This technique's reliability was validated through both physical analysis and non-destructive verification methods, demonstrating its effectiveness as a precise diagnostic tool for complex semiconductor packages.

Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.

Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

With the advent of three-dimensional stacked integrated-circuit (3D IC), the functionality, performance and power of semiconductor devices has been elevated to a new level. At the same time, the analytical techniques used in the evaluation of 3D IC must also advance in capability. Some new methodologies, based on FPGA products, have been developed to analyze 3D IC failures, all using conventional FA equipment and innovative techniques to achieve a short turn-around time and high success rate. A few case studies will be presented to show the effectiveness of the methodologies.

Conductive anodic filament (CAF) formation is a mechanism caused by an electrochemical migration of metals from a metal trace in ICs or in PCBs. This is commonly caused by the moisture build-up in the affected metal terminals in an IC package or PC board caused by critical temperature, high humidity and high voltage gradients conditions. This phenomenon is known to have caused catastrophic field failures on various OEMs electronic components in the past [1,7]. Most published articles on CAF described the formation of the filament in a lateral formation through the glass fiber interfaces between two adjacent metal planes [1-6, 8-12]. One common example is the CAF formation seen between PTH (Plated through Hole) in the laminated substrate with two different potentials causing shorts [1-6, 8-12]. In this paper, the Cu filament grows in a vertical fashion (z-axis formation) creating a vertical plane shorts between the upper and lower metal terminals in a laminated IC package substrate. The copper growth migration does not follow the fiber strands laterally or vertically through them. Instead, it grows through the stress created gaps between the impregnated carbon epoxy fillers from the upper metal trace to the lower metal trace with two different potentials, between the glass fibers. This vertical CAF mechanism creates a low resistive short that was sometimes found to be intermittent in nature. This paper presents some successful failure analysis approaches used to isolate and detect the failure locations for this type of failing devices. This paper also exposes the unique physical appearance of the vertical CAF formation.

The focus of this article is on locating signal-to-ground shorts and plane-to-plane shorts using the time domain reflectometry (TDR) based fault isolation system. The article proposes two comparative techniques for plane-to-plane short location, both based on the secondary information in the TDR data. The first technique looks for the difference in secondary reflections in the TDR waveform and the second looks at the inductance of the current return path, which can be computed in IConnect TDR software. The article presents simple test board example for plane-to-plane short failure location and discusses the results obtained by applying the TDR technique to the measurements of a sample package under test. Locating a signal-to-ground short has been shown to present little difficulty over a comparable open fault locating task. However, with the true impedance profile and planar inductance analyses, the claim of impossibility of locating a plane-to-plane is effectively challenged in this paper.