Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.

Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.