Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).

Today’s VLSI devices are neither designed nor manufactured for space applications in which single event effects (SEE) issues are common. In addition, very little information about the internal schematic and usually nothing about the layout or netlist is available. Thus, they are practically black boxes for satellite manufacturers. On the other hand, such devices are crucial in driving the performance of spacecraft, especially smaller satellites. The only way to efficiently manage SEE in VLSI devices is to localize sensitive areas of the die, analyze the regions of interest, study potential mitigation techniques, and evaluate their efficiency. For the first time, all these activities can be performed using the same tool with a single test setup that enables a very efficient iterative process that reduce the evaluation time from months to days. In this paper, we will present the integration of a pulsed laser for SEE study into a laser probing, laser stimulation, and emission microscope system. Use of this system will be demonstrated on a commercial 8 bit microcontroller.

This paper presents a study about the invasiveness of 1340 nm continuous wave laser used for electrical failure analysis on 28 nm advanced technologies. It underlines the potential laser-induced degradation for deep submicron technologies that could jeopardize analysis results by modifying physical and chemical properties at substructure level. The impact of laser power on transistor morphology and electrical behavior is studied and the results of this study enable us to setup safe experimental conditions.

The Laser Voltage Imaging (LVI) technique, introduced in 2007 [1][2], has been demonstrated as a successful defect localization technique to address problems on advanced technologies. In this paper, several 28nm case studies are described on which the LVI technique and its derivatives provide a real added value to the defect localization part of the Failure Analysis flow. We will show that LVI images can be used as a great reference to improve the CAD alignment overlay accuracy which is critical for advanced technology debug. Then, we will introduce several case studies on 28nm technology on which Thermal Frequency Imaging (TFI) and Second Harmonic Detection (two LVI derivative techniques) allow efficient defect localization.

In this work we present spectrally resolved photon emission microscopy (SPEM) measurements for short-channel FETs acquired through the backside of the Si substrate using InGaAs detector. Two spectrum resolution methods have been used: continuous using a prism and discrete using a set of interference band-pass filters. The photon emission (PE) spectra have been corrected for the background / noise of the detector; they have been calibrated with respect to the system optical transmission function and corrected for the absorption on free carriers in the remaining layer of Si substrate. We discuss all the standardization aspects thoroughly as they are crucial in order to obtain correct device-intrinsic PE spectral information. Finally, we present the spectral results for FET devices operated in various operating conditions.

The Laser Voltage Imaging (LVI) technique [1], introduced in 2009, appears as a very promising approach for Failure Analysis application which allows mapping frequencies through the backside of integrated circuits. In this paper, we propose a new range of application based on the study of the LVI second harmonic for signal degradation analysis. After a theoretical study of the impact of signal degradation on the second harmonic, we will demonstrate the interest of this new approach on two case studies on ultimate technology (28nm). This technique is a new approach of failure analysis that maps timing degradation and duty cycle degradation. In order to confirm the degradations we will use the LVP Technique. The last part is two real case studies on which this LVI second harmonic technique was used to find the root cause of a 28nm process issue.

For Very Deep submicron Technologies, techniques based on the analysis of reflected laser beam properties are widely used. The Laser Voltage Imaging (LVI) technique, introduced in 2009, allows mapping frequencies through the backside of integrated circuit. In this paper, we propose a new technique based on the LVI technique to debug a scan chain related issue. We describe the method to use LVI, usually dedicated to frequency mapping of digital active parts, in a way that enables localization of resistive leakage. Origin of this signal is investigated on a 40nm case study. This signal can be properly understood when two different effects, charge carrier density variations (LVI) and thermo reflectance effect (Thermal Frequency Imaging, TFI), are taken into account.

In this work we present spectrally resolved photon emission microscopy (SPEM) measurements originating from short-channel MOSFETs acquired through the backside of the silicon substrate. Two commonly used detectors have been chosen for the detection of electroluminescence (EL) in the visible and near-infrared spectral regime, namely Si-CCD and InGaAs. As the backside photon emission (PE) inspection is strongly influenced by the absorption of light in a substrate material, the SPEM experiments have been carried out through thinned silicon layers as obtained by mechanical grinding and local focused-ion-beam (FIB) assisted Si material removal. Intrinsic Si absorption (generation of electron-hole pairs) and absorption on free carriers have been modeled to be able to calibrate experimental results and obtain devicerelated PE spectra. The results show no evidences of specific transitions and lead to a conclusion that photon emission from MOSFETs is fully electrical field related.

VLSI internal testing through silicon substrate has been widely studied and techniques like Time Resolved Emission has given impressive results. Nevertheless, Integrated Circuits (IC) are still evolving with more and more complex functions and various kinds of signals that could be split into two main categories: data and control. Controls activate specific block and according to the wide range of different blocks and device complexity, the first analysis task is to check block activity related to control line status. In this paper, we show how Time Resolved Imaging can precisely answer this challenge even in up-to-date technologies at low power supply.

With the innovations in packaging technologies which have taken place over the last decade, new assemblies often include an increasing number of dies inside a single package. This is exactly what was predicted by the More than Moore’s paradigm: as the integration of ICs increases, the heterogeneity of the devices found in a single package increases. As a result, the number of potential failures which can appear at assembly level has increased exponentially. At present, no technique has been able to precisely localize defects which are deep inside a complex package. For this reason, a new technique for failure localization for three-dimensional structures is needed. In this paper the technique proposed, based on the coupling of magnetic measurements and simulations, is applied to a three-dimensional structure to precisely localize the current path which is buried deep inside it. A new method, based on parameters fittings of magnetic simulations, is then applied in order to accurately evaluate the distance between the current and the sensor.

Optical spatial resolution improvement using local focused ion beam (FIB) assisted silicon material removal was investigated. Two types of test structures were chosen for imaging-resolution characterization to be able to use two ways of measuring resolution. Samples of various remaining bulk silicon thicknesses were prepared and characterized in terms of image quality and spatial resolution. The resulting remaining bulk Si thickness was measured using reflectance spectrometry. Images were acquired using halogen-lamp illumination and reflected light detection using a cooled Si-CCD detector. To investigate the image quality at various wavelengths, a set of interference band-pass filters was applied.

The failure localization on analog & mixed mode ICs in functional mode (AC signals) has become more and more challenging in the last few years. Due to an increasing integration and complexity of these devices, the number of defects, especially those named “soft”, raised considerably. The classical Dynamic Laser Stimulation (DLS) techniques showed some limitations when applied to analog & mixedmode ICs. The SDL (Soft Defect Localization) technique [1] based on binary output signal allows us to localize only the most sensitive areas. The defect in this type of circuits, which are very sensitive to the laser beam [2], is often characterized by a weaker sensitivity than that of “healthy” regions. Hence, xVM (Variation Mapping) techniques were introduced to map some parameters in an analog way (the different sensitivity levels are visualized). To date, the T-LSIM technique [3], the Delay and the Phase Variation Mapping techniques were published [4, 5]. We have already had some interesting results by using these techniques [6] but not every “soft” defect case study could be resolved in that way. In this paper we propose to look at some different parameters which characterize an analog signal and can be used as an input for laser mapping. By applying a simple setup, without any additional sophisticated tool, we show on a “golden” commercial IC the added value of this analysis. We also deal with amplifying the weak signal variations induced by the laser beam scan which often are hidden by the high signal variations in analog or mixed-mode ICs.

Defect localization is a very important step in the process of failure analysis for Integrated Circuits. A very important technique, allowing the localization of the defects with a certain degree of precision, is Magnetic Current Imaging. However, this technique has strict limitations related to the working distance and the maximum current magnitude detectable. We overcame these limitations by using a simulation approach, allowing us to sensibly increase the technique resolution and to map currents which are much weaker. This is done by comparing the measurement of the Magnetic Induction Field to a set of simulations of defect assumptions.

Soft defect localization techniques based on laser stimulation have become key techniques for a wide range of FA/debug issues. In this paper, we demonstrate the ability of these techniques to solve critical design issue in mixed-mode device for automotive application which includes analog, logic, RF and power. Utilizing a wide range of laser stimulation techniques, we have determined the most efficient approach for this device to achieve the shortest cycle time. We have established a clear link between fault isolation by laser stimulation techniques and the abnormal behavior of the device with relevant and complete simulation at transistor level.

Failure Analysis has to deal with challenging questions about stored charges in floating gates in Non Volatile Memories (NVM) when reading does not give expected data. Access to this information will help to understand failure mechanisms. A method to measure on-site programmed charges in Flash EEPROM devices is presented. Scanning Capacitance Microscopy (SCM) is used to directly probe the carrier concentration on Floating Gate Transistor (FGT) channels. The methodology permits mapping channels and active regions from the die backside. Transistor charged values (ON/OFF) are measured and localized with a 15 nm resolution. Both preparation and probing methods are discussed. Applications are demonstrated on two different Flash technologies: a two-transistor cell (2T-cell) from Atmel and a one-transistor cell (1T-cell) from STMicroelectronics.

In this paper we report on the application field of Dynamic Laser Stimulation (DLS) techniques to Integrated Circuit (IC) analysis. The effects of thermal and photoelectric laser stimulation on ICs are presented. Implementations, practical considerations and applications are presented for techniques based on functional tests like Soft Defect Localization (SDL) and Laser Assisted Device Alteration (LADA). A new methodology, Delay Variation Mapping (DVM), will also be presented and discussed.

A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical Scanning Probe Microscopy (SPM) based techniques such as Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM) are used to directly probe floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the gate proves to be the key problem, more than the probing technique itself. Applications are demonstrated on 128 kbit EEPROMs from ST Microelectronics and 64 kbit EEPROMs from Atmel.