When considering CDM-like discharge, as it happens frequently in modern high-speed process and test equipment, it is important to avoid a so-called hard discharge in various electrostatic discharge (ESD)-sensitive devices. This study presents the results of experiments that were conducted to characterize the nature of hard discharge in various ESD sample materials: electrical pre-characterization, hard- vs. soft discharge test, oscilloscope measurements of the discharge characteristics, thickness measurements of metal table coatings and mates, and chargeability experiment. The results show that, following the existing standards in semiconductor manufacturing, hard CDM discharge cannot be prevented within the standardized lower resistance bandwidth. Insofar, the related standards ANSI 20.20 and IEC EN 61340-5-1 need to undergo a significant revision in the near future. For failure analysts, the results should be taken into consideration in order to advice useful corrective actions when accompanying client audits or doing ESD risk evaluations, especially within automated process equipment.

If power modules suffer failures, frequently the destruction energy is so high that the component (and also neighbored circuitry) burns down completely. For failure analysis, just some pieces of carbonized leftovers and molten metal balls are available. Of course, no useful analysis on component level is possible in such cases. However, a combination of system-related failure anamnesis and dedicated measurements on new reference systems and surviving parts of the failed system, allows many useful conclusions towards the failure root cause. This paper highlights the most important approaches and questions to be evaluated in such cases.

At ESREF 2008, the paper “Unusual defects, generated by wafer sawing: Diagnosis, mechanisms and how to distinguish from related failures” had won the Best Paper Award. In the meantime, new experiences were collected, related to new methods as laser sawing and its specific ESD risks and additional failure mechanisms as backside damage, charging of foils, pad corrosion and sawing residue damages. This paper explains in detail these failure sources, including detailed explanations on root causes and physical mechanisms as well as important hints for failure analysts how to distinguish related failure signatures from those, which look similar but are of other origin.

The judgment of ESDS risks by direct electrostatic discharge from plastics is a challenge due to the variety of possible discharge scenarios. This paper discusses physical backgrounds of the different discharge scenarios from plastics and tries to rank ESDS related risks. It includes specific hints for ESD prevention in plastics lamination processes as RFID cards, smart cards or contactless money cards, where ESD-sensitive devices (ESDS) are at specific high risk for ESD discharge from plastics. Also further process-related risks and package issues are discussed.

An increasing number of foil capacitors (metallized thin film capacitors, MTFC) are used as filters in power converters. Thus, they are constantly connected between power lines (different phases) or between power lines and ground. However, after some years of operation, severe damage cases were observed, where filter capacitors became extremely hot and started a slow process of outgasing which sometimes is even ended by catastrophic burning. Failure analysis of surviving capacitors of the same kind in neighbor phases identified air inclusions as the cause, which led to internal corona discharge. Useful corona discharge measurements, based on a modification of the well-known partial-discharge (PD) tests, made it possible to assess capacitors on their potential risk of such failures. It turned out that many, even new foil capacitors, started internal corona discharge already underneath their official AC voltage specification.

Anamnesis is known as an important method for pre-diagnosis in medical sciences. In device failure analysis (FA) it is not so far used, yet – especially with regard to system- and application-aspects. As a consequence, a lot of useless rootcause-related FA efforts are done on device level, while the root cause is on system level. Introduced by an illustrative case study, the benefit of a suitable anamnesis is shown as well as the way to do it – by posing the right questions before FA starts. Many FA efforts can be saved or optimized and frequently, a sound anamnesis already may lead towards the root-cause conclusion.

Frequently, Electrical Overstress (EOS) is understood in a similar context like Electrostatic Discharge (ESD). However, when looking deeper, only 3-5% of EOS failure signatures are caused by ESD. The dominant root causes can be found on system level – often inaccessible for the device failure analyst. However, switching procedures and sometimes-hidden inductance loads are the unconsidered and undiscovered problem makers. This paper reviews and highlights these failure mechanisms.

In case of power semiconductor analysis, classical failure localization methods are restricted in application due to thick, closed metal layers and high-dose bulk-Si implants, making backside access difficult. Furthermore, defect traces in power semiconductors are often such severe that no conclusive FA is possible anymore. The new roadmap considers these specialties and shows ways how to deal with them, showing ways to conclusive results.

Since new packaging technologies came up, sensitive failure modes, which were difficult to prove, increased. In many cases, an interaction of bending properties, thermomechanical stress and the material compounds used, cause intermittent failures related to electrical connections. Since any decapsulation might falsify analysis results, non-destructive characterization approaches are of utmost importance for future failure analysis. By means of a typical case study, the capabilities and limitations of a highly developed X-ray tool in such application has been outlined as well as the complexity of root cause findings.

This case study shows a typical example of a manufacturing-chain-induced reliability problem. All participants of the chain do their work within specifications, but, looking at the system level, severe reliability problems have been observed. In order to get back into the system-level process window, several corrective actions are possible. In this case, the most promising approach is an improvement of the stitch bond robustness, combined with a clear user specification.

In many cases it is difficult to distinguish mechanical damage from electrostatic surface impacts. In recent years, several investigations have resulted in publications on ESDFOS (Electrostatic Discharge From Outside to Surface). While the diagnostics of the phenomena have been worked out quite well for wafers with aluminum metallization, no formal studies on ESDFOS impact to copper-metallized wafers have been published. This paper investigates physical features of Cu-metallized wafers artificially exposed to ESDFOS impacts of variable severity, producing an understanding of damage features to more easily facilitate recognition of EDSFOS events.

OBIRCH (Optical Beam Induced Resistivity Change) has been developed to an industrial useable equipment for failure localization. The method turned out to be in certain manner complementary to emission microscopy, detecting failures mainly related to metal wiring problems. At EMPA, EM Microelectronic Marin and CNES Toulouse, first experiences have been collected with this method, using external and CNES-owned OBIRCH equipment. It turned out, that the method does not only help to localize functional failures, but is also most suitable as a reliability-related failure detection tool: OBIRCH-indicates signals at positions where no electrical failure could be seen in standard electrical testing. Analyzing those positions physically, it turned out that indeed significant failure textures have been found, which, however, did not show up electrically, yet. On the other hand, application of OBIRCH on functional devices shows some severe limitations. Thus, OBIRCH might become an interesting in-line tool of the future to detect and to screen reliability-critical failure types, which would pass all present electrical in-line testing on PCMs (Process Control Monitor structures).

Bond pad characterization is usually performed by mechanical cross-sectioning as well as pull and shear tests. However, since all these methods apply mechanical forces to the bond pad, artifacts may result. Focused Ion Beam (FIB) characterization is a mechanically stress-free characterization method, which allows more accurate conclusions regarding the intermetallic behaviour of the bonding area. Some new approaches presented here show how to improve the FIB characterization procedure and to combine it with classical characterization methods.