Highly integrated microelectronic devices drive an ever increasing effort in engineering, manufacturing and failure analysis. Almost all established failure analysis techniques and conventional circuit edit procedures are facing the severe challenges and limits of aggressive downscaling. While device design and manufacturing cooperate closely, failure analysis often is considered as an add-on service upon request. If physical limitations are hard to overcome, extending the application of an established method to promote synergy with other aspects of IC making is one option for future progress. Traditionally circuit edit FIB is a post-fix procedure to allow for fast design changes in the wiring of a chip. Device performance remains unchanged. A different aspect is the deposition of FIB probe pads which permits electrical probing in locations difficult to reach. Probing results in critical regions of a circuit provide tremendous value for general debug or first silicon analysis. Device performance can be monitored. This paper adds a another dimension with new CE and functional chip analysis techniques where device performance can be directly monitored and altered; therefore connecting integrated circuit design, device development and failure analysis for shorter development cycles.

With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

Scan design in modern advanced ICs has enabled the software-based fault diagnosis. It is a powerful tool for localization of defects. However, according to fault diagnosis, there are sometimes many defect candidates and each defect candidate can have many equivalent nets. These nets may be distributed widely, even over the whole chip. Therefore, an additional method of precise defect localization is needed as a complement. In this paper, the TLS method (Thermal Laser Stimulation) is utilized with a simplified setup for this purpose. It shows that the correlation between TLS inspection and scan diagnosis significantly saves analysis time due to the improvement of localization accuracy of the corresponding physical defect.

Modern package technologies like flip-chip, require measurements of transient signals from the chip backside [1], [2]. This is because frontside access is not possible while running a test pattern. This is an established method for CMOS devices and commercial equipment is available. This paper demonstrates the usefulness of a Laser- Voltage-Prober for transient signal measurements from the backside on bipolar-devices.

In this report our SRAM failure analysis flow based on a two metal SRAM and a six transistor cell design is presented. The basic SRAM failures inside the cell array are considered. With standard SRAM tests, the failing cells are detected and a fail bitmap with the physical location of the failing cells is generated. The SRAM failures are classified by the pattern formation of the fail cells. The main focus is on the analysis of single bit failures. In contrast to the often limited physical preparation of SRAMs, a detailed description of the electrical analysis with microprobes, especially of single bit cells, is given. The electrical cell analysis is not limited to hard fails. Soft fails are also accessible. For the different failure classes of the flow, a detailed description of the preparation and physical localization methods e.g. voltage contrast and electrical characterization methods using microprobes is given. Furthermore, analysis results are presented for the different failure classes.