A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

A major yield detractor in wafer final testing and outgoing production testing of a vendor supplied high frequency Gallium Arsenide (GaAs) clock buffer was encountered. The electrical failure modes are open, short, high Idd and gross functional fails. Physical analysis revealed the ohmic contact extrusion with a burst of Gallium from the substrate (GaAs) like a “mushroom” at the ohmic contact of the active layers of the MESFET and the MIM capacitors. The anomaly was not induced by ESD as it was proved by the ESD simulation test. The ESD test showed a much worse catastrophic damage than the extrusion anomaly. EDAX analysis identified high concentration of Ga in the extrusion. Focused Ion Beam (FIB) and Scanning Electron Microscopy (SEM) analysis of the extrusion showed large voids under the contact area at the defect location. Mis-alignment of interconnect metal to ohmic contact (Au-Ge-Ni) and pinholes in ohmic contact metal to active layers in substrate were found throughout the analysis. The pinholes causes the diffusion area to contact directly to the first level gold (Au) interconnect metal (M1). This results in Au-GaAs interdiffusion (mainly Ga) leaving a large void in the bulk substrate similar to kirkendahl voiding. Additional defects were found when the device was electrically biased. The problem was quickly fixed by slightly adjusting an angle in the sputtering process to provide a complete ohmic contact metal coverage on the diffusion contact and subsequently a yield improvement was resulted.