Advanced power generation systems, including advanced ultrasupercritical (A-USC) steam and supercritical carbon dioxide (sCO 2 ) plants operating above 700°C, are crucial for reducing carbon dioxide emissions through improved efficiency. While nickel superalloys meet these extreme operating conditions, their high cost and poor weldability present significant challenges. This study employs integrated computational materials engineering (ICME) strategies, combining computational thermodynamics and kinetics with multi-objective Bayesian optimization (MOBO), to develop improved nickel superalloy compositions. The novel approach focuses on utilizing Ni 3 Ti (η) phase strengthening instead of conventional Ni 3 (Ti,Al) (γ’) strengthening to enhance weldability and reduce costs while maintaining high-temperature creep strength. Three optimized compositions were produced and experimentally evaluated through casting, forging, and rolling processes, with their microstructures and mechanical properties compared to industry standards Nimonic 263, Waspaloy, and 740H. Weldability assessment included solidification cracking and stress relaxation cracking tests, while hot hardness measurements provided strength screening. The study evaluates both the effectiveness of the ICME design methodology and the practical potential of these cost-effective η-phase strengthened alloys as replacements for traditional nickel superalloys in advanced energy applications.

Identifying defects in marginally failed vias has long been a challenge for failure analysis (FA) of state-of-the-art semiconductor integrated circuits. This paper presents two cases where a conventional FA approach is found to not be effective. The first case involves high resistance or marginally open vias. The second case involves early breakdown of large capacitors. The large size of the capacitor and the lack of ways to track electrical flow during diagnosis made it difficult to isolate the defect. The paper shows that conducting atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) are effective techniques for isolation of via-related defects. The SCM technique could be applied to samples without a direct conducting path to the substrate, such as SOI samples. On the other hand, C-AFM allows current imaging as well as I-V characterization whenever a direct conductive path is available.

This paper describes techniques to prepare integrated circuit (IC) samples, containing a Thick Organic Dielectric (TOD) over Cu inductors, for Scanning Electron Microscopy (SEM) or Focused Ion Beam (FIB) editing. Our technique utilizes mechanical polishing and UV laser ablation in lieu of chemical decapsulation and deprocessing.

First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

Infrared Micro Thermography can be applied as electrical fault identification in situations where photon emission is ineffective. Defects, such as certain types of stringers and particles, may conduct without emitting photons in the visible range. Arrayed infrared sensors such as an InSb 512x512 detector, coupled with the appropriate infrared optics can image the heat generated from the leakage site. Heating on the order of a fraction of a degree Kelvin can be observed. The heat signature can be superimposed on a normal optical image of the chip. Several practical examples using this fault identification technique are described.