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Pau-Sheng Kuo
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Proceedings Papers
ISTFA2016, ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis, 125-127, November 6–10, 2016,
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With technology scaling, semiconductor devices have become more prone to damage induced by SEM inspection. In this work, we find that today’s widely-used 0.5KeV SEM can also alter the electrical performance of the devices at 20nm technology node. Vts shift with SEM exposure time on nMOS and pMOS has been studied extensively. The cause of the degradation is the positive charge trapped in the gate oxide during SEM radiation. A conventional UV_eraser for EPROM was applied to SEM-damaged devices. The measurement data show that UV exposure can cure most of SEM-induced damage. In the future, if a regular SEM inspection is followed by nanoprobing device characterization, UV curing or another curing methods is required to recover the electric characteristics of the device before nanoprobing.
Proceedings Papers
Plasma FIB DualBeam Delayering for Atomic Force NanoProbing of 14 nm FinFET Devices in an SRAM Array
ISTFA2015, ISTFA 2015: Conference Proceedings from the 41st International Symposium for Testing and Failure Analysis, 388-400, November 1–5, 2015,
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The result of applying normal xenon ion beam milling combined with patented DX chemistry to delayer state-of-theart commercial-grade 14nm finFETs has been demonstrated in a Helios Plasma FIB DualBeam™. AFM, Conductive-AFM and nano-probing with the Hyperion Atomic Force nanoProber™ were used to confirm the capability of the Helios PFIB DualBeam to delayer samples from metal-6 down to metal-0/local interconnect layer and in under two hours produce a sample that is compatible with the fault isolation, redetection, and characterization capabilities of the AFP. IV (current-voltage) curves were obtained from representative metal-0 contacts exposed by the PFIB+DX delayering process and no degradation to device parameters was uncovered in the experiments that were run. Compared to mechanically delayering samples, the many benefits of using the PFIB+DX process to delayer samples for nano-probing were conclusively demonstrated. Such benefits, include sitespecificity, precise control over the amount of material removed, >100μm square DUT (device under test) area, nm-scale flatness over the DUT area, nm-scale topography between contacts and the surrounding ILD, uniform conductivity across the DUT area, all with no obvious detrimental effects on typical DC device parameters measured by nano-probing.