With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.

This paper demonstrates a breakthrough method of visible laser probing (VLP), including an optimized 577 nm laser microscope, visible-sensitive detector, and an ultimate-resolution gallium phosphide-based solid immersion lens on the 10 nm node, showing a 110 nm resolution. This is 2x better than what is achieved with the standard suite of probing systems using typical infrared (IR) wavelengths today. Since VLP provides a spot diameter reduction of 0.5x over IR methods, it is reasonable, based simply on geometry, to project that VLP using the 577 nm laser will meet the industry needs for laser probing for both the 10 nm and 7 nm process nodes. Based on its high level of optimization, including high resolution and specialized solid immersion lens, it is highly likely that this VLP technology will be one of the last optically-based fault isolation methods successfully used.

A novel method for obtaining diffraction limited high resolution images, and increased signal to noise ratio (SnR), for imaging and probing silicon based complementary metal oxide semiconductor field effect transistor (CMOS, and MOSFET) integrated circuits (IC), is presented. The improved imaging is based on the sub wavelength features’ asymmetric layout, which is dictated by the lithography design rules constrain in CMOS IC and their interactions with polarized light. This asymmetry in layout and the inherent stress engineering on the CMOS IC, produce both dichroism and birefringence in silicon (Si). An elegant design enabled us to obtain two images with orthogonal polarization detection to take advantages of the dichroism and birefringence in Si based CMOS IC. Differential Polarization Image (DPI) is obtained by subtracting the two orthogonal polarization resolved images. On infrared emission microscopes (IREM), DPI in optical imaging mode and DPI plus probing [DPIP] in emission mode, showed 2X or more in terms of optical resolution (imaging mode) and 2X or more SnR (emission-probing mode) improvements. Striking images in probing mode, revealing previously “invisible” emission, were demonstrated.

Circuit Edit and Optical Probe technologies must scale with Intel’s 2 year process cycle and the tick-tock design model. Geometry shrinking combined with revolutionary and evolutionary process changes such-as high-k and metal gate, lower-k interlayer dielectrics, and non-planar devices, make this very challenging. To develop new tools, analytical processes, and validate if the current tool suite can analyze next generation process node and architectures, a special debug block has been designed into Intel’s process test vehicle. In this paper the authors first provide an overview of the Debug Block, we then provide an overview of the LADA, IREM, LVP, TRE, and FIB tools and their corresponding technical challenges for Intel’s next generation microprocessors. Finally we discuss the circuits, layout, and 32nm results.

The paper details a critical innovation for scaling optical probing to access the small feature sizes on advanced silicon process technologies. By using the liquid immersion principle to increase the numerical aperture of the microscope objective, a focused laser spot size of 0.50 µm is achieved for the first time. The liquid immersion objective is the first known application of the immersion principle to backside probing. This system improvement allows optical probing to be used in geometrically scaled processes that would not be accessible without it, and thus will extend the usefulness of laser probing for at least one more generation.