As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

We present a new, non-destructive electrical technique, Power Spectrum Analysis (PSA). PSA as described here uses off-normal biasing, an unconventional way of powering microelectronics devices. PSA with off-normal biasing can be used to detect subtle differences between microelectronic devices. These differences, in many cases, cannot be detected by conventional electrical testing. In this paper, we highlight PSA applications related to aging and counterfeit detection.

Microsystems-enabled photovoltaics (MEPVs) are microfabricated arrays of thin and efficient solar cells. The scaling effects enabled by this technique results in great potential to meet increasing demands for light-weight photovoltaic solutions with high power density. This paper covers failure analysis techniques used to support the development of MEPVs with a focus on the laser beam-based methods of LIVA, TIVA, OBIC, and SEI. Each FA technique is useful in different situations, and the examples in this paper show the relative advantages of each method for the failure analysis of MEPVs.

This paper presents two different case studies that highlight the use of reflected light imaging in laser scanning microscopy. In the first case study, the exact location of defects in metal comb test structures were much easier to detect with reflected light imaging than with thermally-induced voltage alteration (TIVA). This case study also shows visible-wavelength TIVA defect localization using a 532-nm laser. A comparison between 532-nm TIVA and conventional 1320-nm TIVA is made to show the resolution improvement with the visible laser. In the second case study, the cause of a linear string of bit failures was localized easily with backside reflected light imaging. It is observed that the indicated sites matched the light-induced voltage alteration signals and the failing cells in the bit map. In both of the case studies, the reflected light images have proved very helpful in the localization and characterization of failing devices or test structures.

In this paper, we describe a modified soft defect localization (SDL) technique, PSDL (pseudo-soft defect localization), to localize pseudo-soft defects in integrated circuits (ICs). Similar to soft defects, functional failures due to pseudo-soft defects are sensitive to operating parameters (such as voltages, frequencies and temperatures) and/or laser exposures. Pass/fail states in pseudo soft defect failures are, however, not fully reversible after laser exposure or after changing operating parameters. PSDL uses the methodology of conventional SDL and/or TIVA in combination with a new scanning scheme for defect localization. An example will be shown to demonstrate the use of this technique to localize pseudo-soft defects.

Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

We have developed a new scanning laser microscopy methodology, Soft Defect Localization (SDL), that directly locates soft defects from the front side and backside of an IC. The method combines localized laser heating with the pass/fail state of a device to successfully localize soft defects. Subtle, thermally sensitive soft defects can be localized by careful selection of the IC voltage, temperature, and operating frequency. Several examples are shown.

Resistive Interconnection Localization (RIL) is a new scanning laser microscope analysis technique that directly and rapidly localizes defective IC vias, contacts, and conductors from the front side and backside. RIL uses a scanned laser to produce localized thermal gradients in IC interconnections during functional testing. A change in the pass/fail state with localized heating of the IC identifies the failing site. The technique reduces the time to locate a resistive via from months to minutes. The sources of defective vias, the physics of RIL signal generation, and examples of RIL analysis are presented.

Electrical shorting in micro-electro-mechanical systems (MEMS) is a significant production and manufacturing concern. We present a new approach to localizing shorted MEMS devices using Thermally-Induced Voltage Alteration (TIVA) [1]. In TIVA, the shorted, thermally isolated MEMS device is very sensitive to thermal stimulus. The site of the MEMS short will respond as a thermocouple when heated. By monitoring the potential across the shorted MEMS device as a laser scans across the sample, an image showing the location of the thermocouple (short site) can be generated. The TIVA signal for thermally isolated MEMS devices is much higher than that observed for conventional IC interconnections. This results from the larger temperature gradients generated during laser scanning due to little or no substrate heat sinking. The capability to quickly localize shorted MEMS structures is demonstrated by several examples. Thermal modeling of heat distributions is presented and is consistent with the experimental results.

The device physics necessary to gain theoretical insight into the relationship between the bias conditions and the associated electric field for semiconductor structures in various failure conditions such as forward and reverse biased junctions, MOSFET saturation, latchup, and gate oxide breakdown are examined. The relationships are verified by light emission spectra collected from test samples under various bias conditions. Several examples are included that demonstrate the utility and limitations of spectral analysis techniques for defect identification and the associated, non-electric field related information contained in the spectra.

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.