The escalating demand for embedded non-volatile memories (NVM) across automotive, mobile, and personal computer applications necessitates continuous innovation in semiconductor devices. This study focuses on the failure analysis (FA) of split-gate NVM memory, which dominates the landscape of embedded NVM in advanced processes. Presenting a novel approach utilizing nanoprobe techniques on non-accessible floating gate (FG) of NVM, we aim to detect leakage pathways through electron beam absorb current (EBAC) analysis. Through comprehensive experimental analysis and case studies, we demonstrate the efficacy of electrical nanoprobing and innovative sample preparation techniques in understanding the mechanisms behind program and data retention failures in NVM. Our study highlights the significance of precise delayering and nanoprobe techniques on inaccessible FG and identifies potential avenues for future FA methodologies. These findings contribute to a deeper understanding of NVM failure mechanisms, paving the way for enhanced reliability or yield in NVM devices.

Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.

Integrated circuit (IC) de-processing is a crucial step in failure analysis (FA) for defect validation and root cause identification. The commonly used FA de-processing technique is top-down delayering, this is because of faster and easier for sample preparation. However, backside de-processing is occasionally necessary for fault isolation, better root cause understanding, and formulating the failing mechanism such as gate oxide defects, front-end of line (FEOL) defects, back-end of line (BEOL) vertical shorts, high power Ga-N on Silicon (Si) substrate device, etc. This paper introduces an innovative backside de-processing method for ICs utilizing laser ablation by employing a commercial laser decapsulation system. We thin the backside Si substrate via laser ablation and subsequent chemical etching, revealing FEOL defects. Experimental results demonstrate the method's efficiency, offering enhanced sample handling and reduced preparation time. The proposed backside laser de-processing technique proves to be a superior choice compared to conventional methods in terms of success rate, de-processing speed, and cost-effectiveness. This research contributes to advancing FA methodologies by introducing an innovative approach for backside physical FA applications, opening new possibilities for efficient and accurate IC analysis.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically. But sometimes the EFA spot coverage is too big to do nanoprobing analysis. Then further narrow-down is quite critical to identify the suspected structure before nanoprobing is employed. That means there is a gap between global fault isolation and localized device analysis. Under these kinds of situation, PVC and AFP current image are offen options to identify the suspected structure, but they still have their limitation for many soft defect or marginal fails. As in this case, PVC and AFP current image failed to identify the defect in the spot range. To overcome the shortage of PVC and AFP current image analysis, laser was innovatively applied in our current image analysis in this paper. As is known to all, proper wavelength laser can induce the photovoltaic effect in the device. The photovoltaic effect induced photo current can bring with it some information of the device. If this kind of information was properly interpreted, it can give us some clue of the device performance.

As semiconductor technology keeps scaling down, failure analysis and device characterizations become more and more challenging. Global fault isolation without detailed circuit information comprises the majority of foundry EFA cases. Certain suspected areas can be isolated, but further narrow-down of transistor and device performance is very important with regards to process monitoring and failure analysis. A nanoprobing methodology is widely applied in advanced failure analysis, especially during device level electrical characterization. It is useful to verify device performance and to prove the problematic structure electrically, especially for implantation related problems [1] [2]. Implantation related defects, or invisible defects, are the most challenging defect types for the application of fault isolation in all of the failure analysis jobs. The key challenge for these kinds of analyses is to make the defect visible. Sometimes, it is difficult or even impossible to visualize the defective point. Then, sufficient electrical evidence and theory analysis are important to bring the issue to resolution. For these kinds of analyses, a nanoprobing system is a necessary tool to conduct the detailed analysis. Combined with the device physics and electrical theory analysis, nanoprobing can bring out the perfect failure mechanism and problematic process step. There are two popular nanoprobing systems in our lab, one is SEM based and the other is AFM based. Both systems have their advantages and disadvantages in the electrical characterization and fault isolation field. In this paper, an implantation related issue was analyzed. Gross leakage was observed on the failed units as compared with good units. Global fault isolation, TIVA and EMMI failed to find the exclusive hotspot. With the GDS and process analysis, the nanoprobing was employed to the performance check on some of the suspected structures. Finally, the defective location was successfully isolated by nanoprobing. Combined with device physics and electrical analysis, the problematic process was successfully isolated.

This paper explains how the authors used nanoprobing techniques and electrical characterization to trace a die failure to a problem with the photoresist used to mask the wafer for ion implantation. Nanoprobing and leakage current measurements revealed significant differences between the inner and outer fingers of a multi-finger native transistor. Based on simulations, the differences can be attributed to severe scattering at the active edge of the Pwell due to problems with the photoresist, resulting in nonuniform doping profiles and die failure.

This paper describes the debug and analysis process of a challenging case study from wafer foundry which involved a circular patch functional leakage failure that was induced from device parametric drift due to thicker gate oxide with no detection signal from inline monitoring vehicles. It highlights the need for failure analyst to always be inquisitive and to deep dive into the failure symptoms to value-add the fab in discovering the root cause of the failure in challenging situation where information is limited.

As the technology keeps scaling down and IC design becomes more and more complex, failure analysis becomes much more challenging, especially for static fault isolation. For semiconductor foundry FA, it will become even more challenging due to lack of enough information. Static fault isolation is the major global fault isolation methodology in foundry FA and it is difficult to access and trigger the failing signal detected by scan and BIST test, which is widely applied in modern IC design. Because, in most of the time, the normal two pin bias (Vdd and Vss) can only get the comparable IV result between bad unit and the reference unit for function related fail. There are two possibilities from reverse engineering perspective. Firstly, the defect location may not be accessed by the DC bias. Secondly, even if the defect can be accessed, but the defect induced current or voltage change is too small to be differentiated from the overall signal. So it will be concealed in the overall current. However, it is still possible for us to do global fault isolation for the second situation. In this paper, a unit with Iddoff failure was analyzed. Although, no significant IV difference was observed between failed and reference units, a distinct Photon Emission (EMMI) spot was successfully observed in the failed unit. Layout analysis and process analysis on this EMMI spot further confirmed the reality of the emission spot.

It is difficult to simulate functional failures using static analysis tools, therefore, debugging and troubleshooting devices with functional failures present a special challenge for failure analysis (FA) work and often result in a root-cause success rate is quite low. In this paper, the application of advanced FIB circuit edit (CE) processes combined the static FA analysis yielded successful localization of a bipolar junction transistor (BJT) device soft failure. Additional FA techniques were incorporated within the FA flow, resulting in characterization of the electrical behavior of a suspected transistor and detection of an abnormal implant profile within the active area.