The escalating demand for embedded non-volatile memories (NVM) across automotive, mobile, and personal computer applications necessitates continuous innovation in semiconductor devices. This study focuses on the failure analysis (FA) of split-gate NVM memory, which dominates the landscape of embedded NVM in advanced processes. Presenting a novel approach utilizing nanoprobe techniques on non-accessible floating gate (FG) of NVM, we aim to detect leakage pathways through electron beam absorb current (EBAC) analysis. Through comprehensive experimental analysis and case studies, we demonstrate the efficacy of electrical nanoprobing and innovative sample preparation techniques in understanding the mechanisms behind program and data retention failures in NVM. Our study highlights the significance of precise delayering and nanoprobe techniques on inaccessible FG and identifies potential avenues for future FA methodologies. These findings contribute to a deeper understanding of NVM failure mechanisms, paving the way for enhanced reliability or yield in NVM devices.

Failure analysis for gate oxide breakdown is increasingly challenging as technology advances to smaller technology nodes. Previously, the cross-sectional passive voltage contrast (XPVC) technique has been successfully utilized in mature technology nodes to isolate gate oxide breakdown locations in complex polysilicon gate structures of planar transistors. However, as semiconductor technology advances, more intricate transistor structures such as FinFET are employed to improve device performance. This paper focuses on the application of the XPVC technique to metal gate structures and examines the challenges associated with its implementation in advanced technology nodes. We demonstrate the applicability of this method in 14nm FinFET devices in simulated gate oxide breakdown experiments showcasing successful sample preparation for subsequent Transmission Electron Microscopy (TEM) analysis.

Integrated circuit (IC) de-processing is a crucial step in failure analysis (FA) for defect validation and root cause identification. The commonly used FA de-processing technique is top-down delayering, this is because of faster and easier for sample preparation. However, backside de-processing is occasionally necessary for fault isolation, better root cause understanding, and formulating the failing mechanism such as gate oxide defects, front-end of line (FEOL) defects, back-end of line (BEOL) vertical shorts, high power Ga-N on Silicon (Si) substrate device, etc. This paper introduces an innovative backside de-processing method for ICs utilizing laser ablation by employing a commercial laser decapsulation system. We thin the backside Si substrate via laser ablation and subsequent chemical etching, revealing FEOL defects. Experimental results demonstrate the method's efficiency, offering enhanced sample handling and reduced preparation time. The proposed backside laser de-processing technique proves to be a superior choice compared to conventional methods in terms of success rate, de-processing speed, and cost-effectiveness. This research contributes to advancing FA methodologies by introducing an innovative approach for backside physical FA applications, opening new possibilities for efficient and accurate IC analysis.

Cross-sectional analysis plays a crucial role in failure analysis for the identification of root causes associated with implants or junction profiles. Traditionally, this step involves junction staining. Recently, Electron Beam Induced Current (EBIC) analysis has emerged as a valuable alternative, offering the key advantage of visualizing various implantations and junction profiles through non-chemical means. This paper presents an innovative sample preparation technique for cross-sectional EBIC analysis, incorporating an additional step of FIB (Focused Ion Beam) grooving at the target site before cross-sectional polishing. Unlike conventional methods that involve laborious and time-consuming fine cross-sectional polishing, our approach enhances precision and efficiency. With the elimination of the need for extensive polishing, direct access to the target is achieved after rough polishing, thereby expediting the analytical process.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

In this work, we present two case studies on the utilization of advanced nanoprobing on 20nm logic devices at contact layer to identify the root cause of scan logic failures. In both cases, conventional failure analysis followed by inspection of passive voltage contrast (PVC) failed to identify any abnormality in the devices. Technology advancement makes identifying failure mechanisms increasingly more challenging using conventional methods of physical failure analysis (PFA). Almost all PFA cases for 20nm technology node devices and beyond require Transmission Electron Microscopy (TEM) analysis. Before TEM analysis can be performed, fault isolation is required to correctly determine the precise failing location. Isolated transistor probing was performed on the suspected logic NMOS and PMOS transistors to identify the failing transistors for TEM analysis. In this paper, nanoprobing was used to isolate the failing transistor of a logic cell. Nanoprobing revealed anomalies between the drain and bulk junction which was found to be due to contact gouging of different severities.

With technology scaling of semiconductor devices and further growth of the integrated circuit (IC) design and function complexity, it is necessary to increase the number of transistors in IC’s chip, layer stacks, and process steps. The last few metal layers of Back End Of Line (BEOL) are usually very thick metal lines (>4μm thickness) and protected with hard Silicon Dioxide (SiO2) material that is formed from (TetraEthyl OrthoSilicate) TEOS as Inter-Metal Dielectric (IMD). In order to perform physical failure analysis (PFA) on the logic or memory, the top thick metal layers must be removed. It is time-consuming to deprocess those thick metal and IMD layers using conventional PFA workflows. In this paper, the Fast Laser Deprocessing Technique (FLDT) is proposed to remove the BEOL thick and stubborn metal layers for memory PFA. The proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in PFA.

With continuous scaling of CMOS device dimensions, sample preparation for Transmission Electron Microscope (TEM) analysis becomes increasingly important and challenging as the required sample thickness is less than several tens of nanometers. This paper studies the protection materials for FIB milling to increase the success rate of ex-situ ‘lift-out’ TEM sample preparation on 14nm Fin-Field Effect Transistor (FinFET).

With further technology scaling, it becomes increasingly challenging for conventional methods of failure analysis (FA) to identify the cause of a failure. In this work, we present three case studies on the utilization of advanced nanoprobing for SRAM circuit analysis and fault identification on 20 nm technology node SRAM single bit devices. In the first 2 case studies, conventional failure analysis by passive voltage contrast (PVC) failed to identify any abnormality in the known failed bit. In the third case study, an abnormally bright PVC was observed by PVC inspection. In all three case studies, static noise margin of the SRAM bits during hold and read operations were performed to understand the circuit behavior of the failed bit cell. Next, nanoprobing on the individual transistors were performed to determine the failing transistor within the bit and the possible cause of the failure. TEM analysis was performed to identify and verify the failure mechanism.

Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.

With the scaling of semiconductor devices to nanometer range, ensuring surface uniformity over a large area while performing top down physical delayering has become a greater challenge. In this paper, the application of laser deprocessing technique (LDT) to achieve better surface uniformity as well as for fast deprocessing of sample for defect identification in nanoscale devices are discussed. The proposed laser deprocess technique is a cost-effective and quick way to deprocess sample for defect identification and Transmission Electron Microscopy (TEM) analysis.

Top-down, layer-by-layer de-layering inspection with a mechanical polisher and serial cross-sectional Focused Ion Beam (XFIB) slicing are two common approaches for physical failure analysis (PFA). This paper uses XFIB to perform top-down, layer-by-layer de-layering followed by Scanning Electron Microscope (SEM) inspection. The advantage of the FIB-SEM de-layering technique over mechanical de-layering is better control of the de-layering process. Combining the precise milling capability of the FIB with the real-time imaging capability of the SEM enables the operator to observe the de-layering as it progresses, minimizing the likelihood of removing either too much or too little material. Furthermore, real time SEM view during top-down XFIB de-layering is able to provide a better understanding of how the defects are formed and these findings could then be feedback to the production line for process improvement.

SEM-based nanoprobing has proven vital in identifying nonvisual failures through electrical characterization in current FA metrology for fault identification. With eight probes used concurrently, the system could have the ability to obtain other important information such as cell stability as well as the static noise margin (SNM). In this work, the cell stability and SNM at different biasing conditions at low electron beam energy (500eV) of a sub-30 nm technology node SRAM device have been characterized. Bit cell stability, static noise margin test as well as leakage study between two adjacent floating wordines were performed on the SRAM samples. Results show that no significant degradation has been introduced during the data acquisition and imaging processes in the SEM. Good resolution imaging with passive voltage contrast can be achieved with low electron voltage (500eV) throughout the nanoprobing process.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

Electrical Test (ET) structures are used to monitor the health and yield of a process line. With the scaling down of semiconductor devices to nanometer ranges, the number of metal lines and vias increase. In order to simulate the electrical performance of devices and to increase the sensitivity for line health check, ET structures are designed to be more complicated with a larger area. Hence, fault isolation and failure analysis become more challenging. In this paper, the combined technique of Scanning Electron Microscope (SEM) Passive Voltage Contrast (PVC), Nanoprobing technique, and Divide and Conquer Method (DCM) are proposed to locate open failure and high resistance failure in an ET via chain.

The scanning electron microscope (SEM) based nanoprobing technique has established itself as an indispensable failure analysis (FA) technique as technology nodes continue to shrink according to Moore's Law. Although it has its share of disadvantages, SEM-based nanoprobing is often preferred because of its advantages over other FA techniques such as focused ion beam in fault isolation. This paper presents the effectiveness of the nanoprobing technique in isolating nanoscale defects in three different cases in sub-100 nm devices: soft-fail defect caused by asymmetrical nickel silicide (NiSi) formation, hard-fail defect caused by abnormal NiSi formation leading to contact-poly short, and isolation of resistive contact in a large electrical test structure. Results suggest that the SEM based nanoprobing technique is particularly useful in identifying causes of soft-fails and plays a very important role in investigating the cause of hard-fails and improving device yield.

Electrical characterizations were needed to identify the root cause of leakage issues in IC devices. The methodology required was dependent on the failure mode obtained during testing and global or nano-scale isolations had to be implemented accordingly. As such, challenges encountered in sample preparation or due to detection methodology choices for every isolation technique have to be addressed in order to localize the defective sites.

With the scaling down of semiconductor devices to nanometer range, physical failure analysis (PFA) has become more challenging. In this paper, a different method of performing PFA to identify a physical vertical short of intermetal layer in nanoscale devices is discussed. The proposed chemical etch and backside chemical etch PFA techniques have the advantages of sample preparation evenness and efficiency compared to conventional PFA. This technique also offers a better understanding of the failure mechanism and is easier to execute in identifying the vertical short issue.