For VLSI, internal electrical measurements are key steps to solve design debug issues and to perform failure analysis. Due to multiple metal layers, active areas of the chip are only accessible from the backside of the die. The ability of optical contactless techniques to operate through the silicon substrate and the few sample preparation required have widely contributed to promote them as unavoidable tools of the defect localization workflow. Timing issue or unusual consumption can be detected by static and dynamic photon emission analysis. The identification of the emission spots is an essential step of the process. Due to scaling, more and more emission nodes are located within the acquisition area so that large variations of emission intensity can exist. Because of various limitations, former thresholding techniques cannot ensure an exhaustive localization. In this paper, an automated process is reported to locate spots in these complex areas. We will underline the challenge and define application boundaries of this technique.

Recent developments and improvements of laser probing techniques are a good complement to traditional techniques like emission microscopy (static and dynamic) or laser stimulation (also static and dynamic, based on thermal or photoelectric stimulus) for the investigation of failure analysis and diagnostic of integrated circuits. Laser probing techniques have in fact evolved from mainly pulsed approach with high bandwidth [1] to other methodologies based on Continuous Wave (CW) [2,3,4,5]. The bandwidth of these CW approaches is generally lower than pulsed techniques and fine characterization of rising and falling edges or measurement of very small timing shifts can be more difficult or not possible for high speed devices. This bandwidth limitation is most of the time due to the amplification chain. But, CW probing bandwidth is good enough, and continuously improving, to identify directly or indirectly timing issues and to identify bad digital or analog behavior. The setup is also much easier than pulsed laser systems which require complicated synchronization between the system timebase and the device. On this other side new internal analysis modes have been introduced with for example some mapping mode based on frequency analysis or on timing degradation identification through second harmonic analysis [6,7]. At the same time these techniques have pushed the capabilities of a lot of existing tools to investigate low current, low voltage and/or low frequency devices such as analog parts, transmission gates and configurations when the defect cannot be activated at normal or high voltage. Comparison with EMission MIcroscopy (EMMI) in dynamic mode, which can have the higher bandwidth [8] is then possible.

The constant size reduction of the elementary structures in integrated circuits (ICs) and their increasing complexity pushes laser probing techniques to their limits. For old technologies these techniques were powerful tools in defects detection and internal analysis, but now the major limitations of the laser spot size implies the understanding of the complex information contained in the reflected beam when it covers an area of multiple elementary structures. Knowing the contribution of each elementary structure covered by the laser spot in the reflected laser beam is the key to have a good analysis and interpretation of the probed area. In this paper we will expose the different parameters that modify the intensity of a laser beam and the contribution of a basic structure covered by a big laser spot size as well as the systematic approach we have built to deal with this challenging reflected laser probe signal from multiple elementary substructures in very deep submicron technologies.

Time Resolved Imaging (TRI) acquisitions allow precise timing analysis of emission spots. Up to date technologies deeply challenge their isolation by hiding the weak ones, under sizing or over sizing visually detectable emission spots and finally by jeopardizing timing resolution. We report on an algorithm based on 1 and 2D signal processing tools which automates the identification of emission sites and optimizes separation between noise and useful signal, even for weak spots surrounding strong emission areas. The application of the algorithm on several sets of data from different types of devices and their results are also discussed.

From a designer point of view, the analysis of a failure root cause can quickly become a nightmare if the number of hypothesis provided by a simulation tool is too high. To help solving this kind of problem the use of physical probing measurement can reduce drastically the number of assumptions made by the simulation by invalidating certain hypotheses. The purpose of this paper is to add to the simulation a new source of information based on light emission to solve this kind of problem. Virtual logic diagram computation is able to provide several hypotheses of fault for a given node and data coming from Time Resolved Imaging (TRI) measurement allows extraction of transition pattern for a given node where the assumption has been established. The cross-referencing of this information aims at eliminating wrong hypotheses and making the simulation more reliable.

Dynamic Laser Stimulation (DLS) techniques proved to be very efficient in soft defect localization bringing a lot of information about the device internal behavior. We need to use external parameter measurements such as frequency, delay, voltage etc to perform these techniques. So they can't be used to study internal signal propagation problems in latched device since signals are resynchronized. We will show that we can use the power analysis coupled with DLS techniques set up to characterize soft defect when we don't have a direct access to monitored signal propagation such as in some transistor transition issues. Laser stimulation in addition of power analysis is used to decrypt security codes in security chip, but in failure analysis it is a new way to reach internal information in order to localize soft defects.

HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. They are crucial components for the development of base stations in the telecommunications networks and for civil, defense and space radar applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by standard (Visible-NIR) and Infrared (range of wavelength: 3-5 µm) electroluminescence techniques. Its complementarities and efficiency have been demonstrated through two case studies.

Limitations of backside optical techniques for failure analysis of dynamically activated devices have underlined the need to extend the capabilities of Dynamic Laser Stimulation techniques (DLS). DLS techniques provide a precise localization of the dynamically failing area, but it lacks timing information as the fault is often related to a specific test vector. Optical probing techniques such as TRE and LVP [1, 2] are hardly applicable on cases with long test loop and for which no preliminary information is available on the time window of interest. Defect localization and electrical tests can be coupled in order to provide more accurate information about the failure, especially vector information in addition to x and y localization. We have developed a Full Dynamic Laser Stimulation (F-DLS) approach based on laser modulation by electro optic modulator to face this challenge. The purpose of this paper is to present DLS limitations, our motivations, comparisons with other DLS extensions, FDLS implementation on our system, application example and future F-DLS developments.

HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. As well as the improvement of the MMIC performances, the localization of the defects linked with hot electron and the failure analysis of these devices are very challenging. To face these challenges, we have developed a complete approach, without degrading the component, based on front side failure analysis by UV electroluminescence or UV light emission. Its feasibility and efficiency have been demonstrated through two case studies. So, a specific UV microscopy technique has been developed and is presented in this paper.

Modulated Thermal Laser Stimulation (M-TLS) has been established as a key technique to accurately localize defects at elementary structure level, in deep submicron technologies. It has been achieved by Thermal Time Constant analysis (TTC) which allows the study of thermal exchange dynamics. In this paper, we demonstrate for the first time the efficiency of this technique on 45 nm Back End Of the Line (BEOL) defective test structure on image mode, and we underline the efficiency of the developed technique to differentiate artifacts from true defects in 45 nm BEOL structures.

III-V HBT (Heterojunction Bipolar Transistor) and HEMT (High Electron Mobility Transistor) are playing a key role for power and RF low noise applications. As well as the improvement of the MMIC performances, the localization of the defects and the failure analysis of these devices are very challenging. Active area thickness is only few nanometers, backside failure localization is mandatory because of thermal drain or metal bridge covering the front side, materials involved might be of ultimate hardness and/or high chemical sensitivity while failure mechanisms strongly differ from Si technology ones. To face these challenges, we have developed a complete approach, without degrading the component, based on backside failure analysis by electroluminescence. Its efficiency and completeness have been demonstrated through case studies.

Soft defects localization by laser techniques on dynamically working ICs is widely used for Failure Analysis (FA). In this context, many AC signal-oriented analysis methods have been introduced to date (SDL, LADA…) or are under development (xVM…). Sophisticated tools are available to localize these kinds of failures but not every FA laboratory has them. By fully exploiting the capabilities of static localization tools, it is possible to deal with timing issues. In this paper, we propose a novel application of the OBIRCh amplifier related to the timing issues on a real case study (mixed-mode device). This novel and very simple application makes the analysis flow time-attractive and enlarges the application field of mapping techniques on the existing tools.

A key point to guarantee electronic device quality is device qualification. This part of the process is a significant contributor to the time and cost of the development and production of any electronic device. A device is required to perform a task and its operational lifetime is a key issue for the end user. The more sensitive the qualification technique is, the faster marginalities in the device parameters could be observed. Dynamic Laser Stimulation techniques fill this requirement and could be used in conjunction with traditional qualification procedures.

Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.

Infra-red Thermal Laser Stimulation (TLS) signatures obtained on semiconductor materials can be difficult to interpret and to distinguish from signatures from metallic materials. Investigations presented here consist in the study of TLS signals on unsilicided/silicided polycrystalline and diffused silicon resistors of 0.18µm technology. The influence of each process parameter on the TLS signal has been observed and evaluated from the front and back side of the circuit. This allowed us to quantify the effect of the silicon substrate thickness on TLS signal detection and to determine the ideal silicon thickness for sample preparation. This study also completes our methodology based on the TCR parameter which aims at improving defect localization in the depth (Z) of circuitry. As it will be shown through failure analysis case studies, this methodology increases the physical analysis success rate and reduces the turnaround time.

Ultra-short pulse laser ablation is applied to IC backside sample preparation. It is contact-less, non-thermal, precise and can ablate the various types of material present in IC packages. This study concerns the optimization of ultra-short pulse laser ablation for silicon thinning. Uncontrolled silicon roughness and poor uniformity of the laser thinned cavity needed to be tackled. Special care is taken to minimize the silicon RMS roughness to less than 1µm. Application to sample preparation of 256Mbit devices is presented.

We developed a system and a method to characterize the magnetic field induced by circuit board and electronic component, especially integrated inductor, with magnetic sensors. The different magnetic sensors are presented and several applications using this method are discussed. Particularly, in several semiconductor applications (e.g. Mobile phone), active dies are integrated with passive components. To minimize magnetic disturbance, arbitrary margin distances are used. We present a system to characterize precisely the magnetic emission to insure that the margin is sufficient and to reduce the size of the printed circuit board.

Several considerations related to the implementation of the thermal laser stimulation method (OBIRCH, TIVA) in a failure analysis laboratory will be discussed. At the CNES (French Space Agency), we implemented this method on a dual system which includes an emission microscope and a laser-scanning microscope. The amplifier used for amplifying the weak voltage or current variations caused by thermal laser stimulation was shown to be a key factor. The design of such a low noise, high gain and fast voltage amplifier is described. From a 3D finite element ANSYS model of the thermal laser stimulation effect combined with three practical case studies we show that thermal laser stimulation is a rapid and precise method for localizing metallic short type faults in ICs. In order to interpret the thermal laser stimulation signal, a simple CMOS inverter model is also presented.

Emission microscopy and thermal laser stimulation (OBIRCH, TIVA) are two key methods for backside failure analysis. They are both dedicated for localizing current leakage faults in ICs. The complementary relationship of these two techniques is illustrated through six practical case studies. Thermal laser stimulation was able to precisely and directly localize defects such as shorts in the IC’s metallic elements that where not readily detectable by emission microscopy. The case studies also illustrate the ability of thermal laser stimulation to detect and physically localize defects in the IC’s polysilicon layers and silicon substrate.

To deal with failure analysis laboratory tasks, we have developed a modular and smart test system. We demonstrate that Smart Testing Interface can keep a device in the proper electrical state for defect localization. It is a key part of our system and can be easily adapted on a wide range of electrical testers. It offers a unique combination of a slave and a standalone mode. In slave mode, it has a non-disruptive interface between the tester and the component. In stand-alone mode, it is an electrical stimuli generator that can keep the device under test in the correct internal electrical state during IC defect localization. A battery or a power supply powers it up. It can be readily carried in stand-alone mode from one tool to another tool. In stand-alone mode, it has a range of eight hours or more according to the battery capacity and device consumption. We will review a failure analysis laboratory needs and then describe test solutions with our Modular and Smart Test System and a 344 I/O Smart Testing Interface. It is used for EMMI and OBIRCH applications on PHEMOS 1000.