The ability to precisely remove the internal structures of a semiconductor device, layer-by-layer, is a necessity for semiconductor research and failure analysis investigation. Currently, numerous techniques are used, such as mechanical polishing, chemical etching, and gas assisted plasma focused ion beam (FIB) milling. However, all of these techniques have limitations in that they are unable to: (1) delayer a millimeter-scale area with nanometer-scale uniformity, (2) rapidly remove thick (>300 nm) device layers, or (3) perform automatic and accurate end pointing, which is challenging on thin (≤300 nm) device layers.

We describe a fully integrated solution for millimeter-scale delayering of both logic and memory semiconductor devices. The flatness of the delayered device is controlled by an artificial intelligence algorithm, which uses feedback from multiple analytical detectors to control milling parameter adjustments in real time. The result is the precise removal of device layers and a highly planar surface.