Failure analysis of advanced semiconductor devices demands fast and accurate examination from the bulk to the specific area of the defect. Consequently, nanometer resolution and below is critical for finding defects. This work presents the use of argon ion milling methods for multiple length scale sample preparation, micrometer to sub-ångström, without sample preparation- induced artifacts for correlative SEM and TEM failure analysis. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 20 nm are obtained.

The size of devices on state-of-the-art integrated circuits continues to decrease with each technology node, which drives the need to continually improve the resolution of electrical failure analysis techniques. Solid immersion lenses are commonly used in combination with infrared light to perform analysis from the backside of the device, but typically only have resolutions down to ~200 nm. Improving resolution beyond this requires the use of shorter wavelengths, which in turn requires a silicon thickness in the 2 to 5 µm range. Current ultra-thinning techniques allow consistent thinning to ~10 µm. Thinning beyond this, however, has proven challenging. In this work, we show how broad beam Ar ion milling can be used to locally thin a device’s backside silicon until the remaining silicon thickness is < 5 µm.

The semiconductor industry recently has been investigating new specimen preparation methods that can improve throughput while maintaining quality. The result has been a combination of focused ion beam (FIB) preparation and ex situ lift-out (EXLO) techniques. Unfortunately, the carbon support on the EXLO grid presents problems if the lamella needs to be thinned once it is on the grid. In this paper, we show how low-energy (< 1 keV), narrow-beam (< 1 μm diameter) Ar ion milling can be used to thin specimens and remove gallium from EXLO FIB specimens mounted on various support grids.

A packaged device based on a ball grid array or other design presents a challenge to the failure analyst. Accessing one of the metal levels from the topside requires decapsulation by either a wet, predominantly dry (RIE) or a completely dry (mechanical) treatment. To reveal the details of the gate including the gate oxide, new approaches to selective etch delineation by RIE are required. This article presents an automated sample preparation method for packaged microelectronic materials by combining plasma cleaning, ion beam etching, reactive ion etching and ion beam sputter coating. A single etch gas chemistry was effective in phase delineation by RIE. Future work to further delineate the gate oxides could support accurate metrology by means of FESEM rather than field emission transmission electron microscope.

The SiLK resins, composed of aromatic hydrocarbons, are a family of highly cross-linked thermoset polymers with isotropic dielectric properties. Patterning of SiLK for high aspect ratio copper interconnects has depended on reactive ion etching with oxygen/nitrogen gas mixtures. Reactive ion etching is therefore also accomplished with reducing plasmas such as nitrogen/hydrogen. An additional plasma cleaning step can be inserted after the reactive ion etching (RIE) step, so that any residual contamination is removed prior to imaging or final sputter coating. Automated sample preparation of microelectronic materials containing high and low-k dielectrics for FESEM is accomplished in this article by combining these techniques: plasma cleaning, ion beam etching, and reactive ion etching. A single RIE chemistry was effective in etching both dielectrics as well as delineating the other phases present.

Standard analytical practice in the semiconductor industry depends on fast, efficient and reliable sample preparation prior to FESEM. “In lens” imaging technology and orientation mapping (EBSD) demand sample surfaces free of physical damage and residual contamination. An integrated preparation tool has been developed that incorporates the functionality necessary for argon – oxygen plasma cleaning, ion beam etching (IBE), reactive ion beam etching (RIBE), reactive ion etching (RIE), and ion beam sputter coating (IBSC). Control, monitoring and sequential automation of the processes is accomplished through a novel combination of software and hardware. FESEM results for Al and Cu based microelectronic materials will be discussed, as well as EBSD results for bulk metals. Improvements in throughput and subsequent materials characterization will be demonstrated.